diff options
| author | Benjamin Kramer <benny.kra@googlemail.com> | 2017-12-18 19:21:56 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2017-12-18 19:21:56 +0000 |
| commit | efc7c88ea8d0f5b0fa320c61ccb41ec2303aedbf (patch) | |
| tree | 030850159ff5702742093390f74bac42c880388d /llvm/test/CodeGen/PowerPC/setcc-logic.ll | |
| parent | 0fa52c7db13bd0dec0b64776f57d7229f2e96486 (diff) | |
| download | bcm5719-llvm-efc7c88ea8d0f5b0fa320c61ccb41ec2303aedbf.tar.gz bcm5719-llvm-efc7c88ea8d0f5b0fa320c61ccb41ec2303aedbf.zip | |
[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.
This has the same issue as the early pass disabled in r321010.
llvm-svn: 321013
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/setcc-logic.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/setcc-logic.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll index d27538fb8d5..3b9b5228fa4 100644 --- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll +++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s +; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true | FileCheck %s define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_clear: |
