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* [DAGCombiner] Improve X div/rem Y fold if single bit element typeDavid Bolvansky2018-10-304-112/+25
| | | | | | | | | | | | | | Summary: Tests by @spatel, thanks Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: sdardis, atanasyan, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D52668 llvm-svn: 345575
* Relax fast register allocator related test cases; NFCMatthias Braun2018-10-294-14/+14
| | | | | | | | | | | | | - Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
* Regenerate FP_TO_INT tests.Simon Pilgrim2018-10-272-558/+2939
| | | | | | Precursor to fix for PR17686 llvm-svn: 345453
* [MIPS GlobalISel] Legalize constantsPetar Jovanovic2018-10-172-0/+272
| | | | | | | | | | Legalize s1, s8, s16 and s64 G_CONSTANT for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D53077 llvm-svn: 344684
* [mips][micromips] Fix how values in .gcc_except_table are calculatedAleksandar Beserminji2018-10-161-0/+37
| | | | | | | | | | | | | When a landing pad is calculated in a program that is compiled for micromips, it will point to an even address. Such an error will cause a segmentation fault, as the instructions in micromips are aligned on odd addresses. This patch sets the last bit of the offset where a landing pad is, to 1, which will effectively be an odd address and point to the instruction exactly. Differential Revision: https://reviews.llvm.org/D52985 llvm-svn: 344591
* [LegalizeVectorTypes] When widening the result of a bitcast from a scalar ↵Craig Topper2018-10-121-12/+12
| | | | | | | | | | type, use a scalar_to_vector to turn the scalar into a vector intead of a build vector full of mostly undefs. This is more consistent with what we usually do and matches some code X86 custom emits in some cases that I think I can cleanup. The MIPS test change just looks to be an instruction ordering change. llvm-svn: 344422
* [mips] Mark fmaxl as a long double emulation routineStefan Maksimovic2018-10-121-0/+25
| | | | | | | | | | | | | | | | | | Failure was discovered upon running projects/compiler-rt/test/builtins/Unit/divtc3_test.c in a stage2 compiler build. When compiling projects/compiler-rt/lib/builtins/divtc3.c, a call to fmaxl within the divtc3 implementation had its return values read from registers $2 and $3 instead of $f0 and $f2. Include fmaxl in the list of long double emulation routines to have its return value correctly interpreted as f128. Almost exact issue here: https://reviews.llvm.org/D17760 Differential Revision: https://reviews.llvm.org/D52649 llvm-svn: 344326
* [DAG] Fix Big Endian in Load-Store forwardingNirav Dave2018-10-111-23/+47
| | | | | | | | | | | | | | Summary: Correct offset calculation in load-store forwarding for big-endian targets. Reviewers: rnk, RKSimon, waltl Subscribers: sdardis, nemanjai, hiraditya, jrtc27, atanasyan, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D53147 llvm-svn: 344272
* [DAGCombine] Improve Load-Store ForwardingNirav Dave2018-10-104-36/+26
| | | | | | | | | | | | | | | | | | Summary: Extend analysis forwarding loads from preceeding stores to work with extended loads and truncated stores to the same address so long as the load is fully subsumed by the store. Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are deleted as they've no longer seem to be relevant. Reviewers: RKSimon, rnk, kparzysz, javed.absar Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D49200 llvm-svn: 344142
* [MIPS GlobalISel] Legalize i64 addPetar Jovanovic2018-10-082-0/+51
| | | | | | | | | | Custom legalize s64 G_ADD for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D52652 llvm-svn: 344007
* [mips] Remove -allow-deprecated-dag-overlap flag from tests. NFCSimon Atanasyan2018-10-038-127/+146
| | | | | | | Fix DAG check statements in MIPS codegen tests to remove -allow-deprecated-dag-overlap flag. llvm-svn: 343730
* [mips] Generate tests expectations using update_llc_test_checks. NFCSimon Atanasyan2018-10-014-598/+1865
| | | | | | | Generate tests expectations using update_llc_test_checks and reduce number of "check prefixes" used in the tests. llvm-svn: 343485
* [MIPS GlobalISel] Lower i64 argumentsPetar Jovanovic2018-09-281-0/+106
| | | | | | | | | | | | | Lower integer arguments larger then 32 bits for MIPS32. setMostSignificantFirst is used in order for G_UNMERGE_VALUES and G_MERGE_VALUES to always hold registers in same order, regardless of endianness. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D52409 llvm-svn: 343315
* [Mips][FastISel] Fix selectBranch on icmp i1Petar Jovanovic2018-09-241-0/+189
| | | | | | | | | | | | | | The r337288 tried to fix result of icmp i1 when its input is not sanitized by falling back to DagISel. While it now produces the correct result for bit 0, the other bits can still hold arbitrary value which is not supported by MipsFastISel branch lowering. This patch fixes the issue by falling back to DagISel in this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D52045 llvm-svn: 342884
* [mips][microMIPS] Extending size reduction pass with MOVEPSimon Atanasyan2018-09-192-0/+115
| | | | | | | | | | | The patch extends size reduction pass for MicroMIPS. Two MOVE instructions are transformed into one MOVEP instrucition. Patch by Milena Vujosevic Janicic. Differential revision: https://reviews.llvm.org/D52037 llvm-svn: 342572
* [MIPS] Fix illegal type assert in single-float modeSimon Atanasyan2018-09-111-0/+52
| | | | | | | | | | | | An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in single-float mode. This would trigger an "Unexpected illegal type!" assert. Patch by Dan Ravensloft. Differential revision: https://reviews.llvm.org/D51810 llvm-svn: 341952
* [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instructionSimon Atanasyan2018-09-111-4/+4
| | | | | | | | | | | | | | | | | | | | | MIPS ISAs start to support third operand for the `rdhwr` instruction starting from Revision 6. But LLVM generates assembler code with three-operands version of this instruction on any MIPS64 ISA. The third operand is always zero, so in case of direct code generation we get correct code. This patch fixes the bug by adding an instruction alias. The same alias already exists for 32-bit ISA. Ideally, we also need to reject three-operands version of the `rdhwr` instruction in an assembler code if ISA revision is less than 6. That is a task for a separate patch. This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861) Differential revision: https://reviews.llvm.org/D51773 llvm-svn: 341919
* [MIPS GlobalISel] Select icmpPetar Jovanovic2018-09-104-0/+1063
| | | | | | | | | | Select 32bit integer compare instructions for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51489 llvm-svn: 341840
* [mips] Disable the selection of mixed microMIPS/MIPS codeSimon Atanasyan2018-09-031-2/+1
| | | | | | | | | | | | | This patch modifies hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods of the MipsSubtarget class so only one can be true at any one time. That prevents the selection of microMIPS and MIPS instructions and patterns that are defined in TableGen files at the same time. A few new patterns and instruction definitions hae been added to keep test cases passed. Differential revision: https://reviews.llvm.org/D51483 llvm-svn: 341338
* [mips] Fix `mtc1` and `mfc1` definitions for microMIPS R6Simon Atanasyan2018-08-311-0/+68
| | | | | | | | | | | | | | | The `mtc1` and `mfc1` definitions in the MipsInstrFPU.td have MMRel, but do not have StdMMR6Rel tags. When these instructions are emitted for microMIPS R6 targets, `Mips::MipsR62MicroMipsR6` nor `Mips::Std2MicroMipsR6` cannot find correct op-codes and as a result the backend uses mips32 variant of the instructions encoding. The patch fixes this problem by adding the StdMMR6Rel tag and check instructions encoding in the test case. Differential revision: https://reviews.llvm.org/D51482 llvm-svn: 341221
* [mips] Fix microMIPS unconditional branch offset handlingSimon Atanasyan2018-08-291-0/+98
| | | | | | | | | | | | | | MipsSEInstrInfo class defines for internal purpose unconditional branches as Mips::B nad Mips:J even in case of microMIPS code generation. Under some conditions that leads to the bug - for rather long branch which fits to Mips jump instruction offset size, but does not fit to microMIPS jump offset size, we generate 'short' branch and later show an error 'out of range PC16 fixup' after check in the isBranchOffsetInRange routine. Differential revision: https://reviews.llvm.org/D50615 llvm-svn: 340932
* [mips] Involves microMIPS's jump in the analyzable branch setSimon Atanasyan2018-08-291-5/+2
| | | | | | | | | Involves microMIPS's jump in the analyzable branch set to reduce some code patterns. Differential revision: https://reviews.llvm.org/D50613 llvm-svn: 340931
* [mips] Prevent shrink-wrap for BuildPairF64, ExtractElementF64 when they use $spVladimir Stefanovic2018-08-292-0/+182
| | | | | | | | | | | | | | | | For a certain combination of options, BuildPairF64_{64}, ExtractElementF64{_64} may be expanded into instructions using stack. Add implicit operand $sp for such cases so that ShrinkWrapping doesn't move prologue setup below them. Fixes MultiSource/Benchmarks/MallocBench/cfrac for '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfpxx -mnan=2008' and '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfp64 -mnan=2008 -mno-odd-spreg'. Differential Revision: https://reviews.llvm.org/D50986 llvm-svn: 340927
* [DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the ↵Craig Topper2018-08-283-31/+18
| | | | | | | | | | | | | | | | | | | resulting load is legal for the target. Summary: I'm not sure if this patch is correct or if it needs more qualifying somehow. Bitcast shouldn't change the size of the load so it should be ok? We already do something similar for stores. We'll change the type of a volatile store if the resulting store is Legal or Custom. I'm not sure we should be allowing Custom there... I was playing around with converting X86 atomic loads/stores(except seq_cst) into regular volatile loads and stores during lowering. This would allow some special RMW isel patterns in X86InstrCompiler.td to be removed. But there's some floating point patterns in there that didn't work because we don't fold (f64 (bitconvert (i64 volatile load))) or (f32 (bitconvert (i32 volatile load))). Reviewers: efriedma, atanasyan, arsenm Reviewed By: efriedma Subscribers: jvesely, arsenm, sdardis, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, arichardson, jrtc27, atanasyan, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50491 llvm-svn: 340797
* [MIPS GlobalISel] Legalize i8 and i16 addPetar Jovanovic2018-08-262-3/+261
| | | | | | | | | | | | Legalize G_ADD for types smaller than i32. LegalizationArtifactCombiner replaces extend instructions with appropriate bitwise instructions. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51213 llvm-svn: 340697
* [DAGCombiner][Mips] Don't combine bitcast+store after LegalOperations when ↵Craig Topper2018-08-242-4/+8
| | | | | | | | | | | | | | the store is volatile, if the resulting store isn't Legal Previously we allowed the store to be Custom. But without knowing for sure that the Custom handling won't split the store, we shouldn't convert a volatile store. We also probably shouldn't be creating a store the requires custom handling after LegalizeOps. This could lead to an infinite loop if the custom handling was to insert a bitcast. Though I guess isStoreBitCastBeneficial could be used to block such a loop. The test changes here are due to the volatile part of this. The stores in the test are all volatile and i32 stores are marked custom, So we are no longer converting them This is related to D50491 where I was trying to allow some bitcasting of volatile loads Differential Revision: https://reviews.llvm.org/D50578 llvm-svn: 340626
* [MIPS GlobalISel] Lower i8 and i16 argumentsPetar Jovanovic2018-08-231-0/+288
| | | | | | | | | | | | Lower integer arguments smaller than i32. Support both register and stack arguments. Define setLocInfo function for setting LocInfo field in ArgLocs vector. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51031 llvm-svn: 340572
* [mips] Handle missing CondCodesStefan Maksimovic2018-08-221-0/+63
| | | | | | | | | | | | | | | | | | | | Add patterns for unhandled CondCode enumerables: SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE. Stated at the ISD::CondCode enum declaration: `All of these (except for the 'always folded ops') should be handled for floating point.` Add patterns which use these nodes, same as corresponding 'ordered' CondCode nodes. Referring to 'Ordered means that neither operand is a QNAN' we assume it is safe to match ex. SETLT node to the same instruction as SETOLT. Differential Revision: https://reviews.llvm.org/D50757 llvm-svn: 340392
* [MIPS GlobalISel] Select bitwise instructionsPetar Jovanovic2018-08-215-0/+896
| | | | | | | | | | Select bitwise instructions for i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D50183 llvm-svn: 340258
* [mips] Handle branch expansion corner casesAleksandar Beserminji2018-08-073-0/+153
| | | | | | | | | | | | When potential jump instruction and target are in the same segment, use jump instruction with immediate field. In cases where offset does not fit immediate value of a bc/j instructions, offset is stored into register, and then jump register instruction is used. Differential Revision: https://reviews.llvm.org/D48019 llvm-svn: 339126
* [MIPS GlobalISel] Select global addressPetar Jovanovic2018-08-015-0/+193
| | | | | | | | | | Select G_GLOBAL_VALUE for position dependent code. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49803 llvm-svn: 338499
* [DAGCombiner] Teach DAG combiner that A-(B-C) can be folded to A+(C-B)Craig Topper2018-07-281-24/+24
| | | | | | | | This can be useful since addition is commutable, and subtraction is not. This matches a transform that is also done by InstCombine. llvm-svn: 338181
* [mips] Sign extend i32 return values on MIPS64Stefan Maksimovic2018-07-267-38/+37
| | | | | | | | | | | | | Override getTypeForExtReturn so that functions returning an i32 typed value have it sign extended on MIPS64. Also provide patterns to get rid of unneeded sign extensions for arithmetic instructions which implicitly sign extend their results. Differential Revision: https://reviews.llvm.org/D48374 llvm-svn: 338019
* [MIPS GlobalISel] Lower pointer argumentsPetar Jovanovic2018-07-255-0/+323
| | | | | | | | | | | | Add support for lowering pointer arguments. Changing type from pointer to integer is already done in MipsTargetLowering::getRegisterTypeForCallingConv. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49419 llvm-svn: 337912
* [mips] Fix local dynamic TLS with Sym64Simon Atanasyan2018-07-241-4/+5
| | | | | | | | | | | | | | | | For the final DTPREL addition, rather than a lui/daddiu/daddu triple, LLVM was erronously emitting a daddiu/daddiu pair, treating the %dtprel_hi as if it were a %dtprel_lo, since Mips::Hi expands unshifted for Sym64. Instead, use a new TlsHi node and, although unnecessary due to the exact structure of the nodes emitted, use TlsHi for local exec too to prevent future bugs. Also garbage-collect the unused TprelLo and TlsGd nodes, and TprelHi since its functionality is provided by the new common TlsHi node. Patch by James Clarke. Differential revision: https://reviews.llvm.org/D49259 llvm-svn: 337827
* Fix typo in test/CodeGen/Mips/dins.llThomas Anderson2018-07-231-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D49704 llvm-svn: 337771
* [mips] Add more checks to the tls.ll test case. NFCSimon Atanasyan2018-07-231-49/+106
| | | | llvm-svn: 337705
* [mips] Move out the WrapperPat declaration from the NotInMicroMips predicateSimon Atanasyan2018-07-212-0/+88
| | | | | | | | | | | | | | | This is a follow-up to the rL335185. Those commit adds some WrapperPat patterns for microMIPS target. But declaration of the WrapperPat class is under the NotInMicroMips predicate and microMIPS patterns cannot be selected because predicate (Subtarget->inMicroMipsMode()) && (!Subtarget->inMicroMipsMode()) is always false. This change move out the WrapperPat class declaration from the NotInMicroMips predicate and enables microMIPS WrapperPat patterns. Differential revision: https://reviews.llvm.org/D49533 llvm-svn: 337646
* [mips] Fix predicate for the MipsTruncIntFP patternSimon Atanasyan2018-07-181-1/+2
| | | | | | | | | This is a follow-up to the rL337171. This patch fixes regression introduced by the r337171 and enables MipsTruncIntFP pattern. Differential revision: https://reviews.llvm.org/D49469 llvm-svn: 337392
* [Mips][FastISel] Fix handling of icmp with i1 typePetar Jovanovic2018-07-172-2/+15
| | | | | | | | | | | The Mips FastISel back-end does not extend i1 values while lowering icmp. Ensure that we bail into DAG ISel when handling this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D49290 llvm-svn: 337288
* [DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELTSimon Pilgrim2018-07-171-500/+260
| | | | | | | | If we are only extracting vector elements via EXTRACT_VECTOR_ELT(s) we may be able to use SimplifyDemandedVectorElts to avoid unnecessary vector ops. Differential Revision: https://reviews.llvm.org/D49262 llvm-svn: 337258
* [MIPS GlobalISel] Select instructions to load and store i32 on stackPetar Jovanovic2018-07-164-0/+219
| | | | | | | | | | | Add code for selection of G_LOAD, G_STORE, G_GEP, G_FRAMEINDEX and G_CONSTANT. Support loads and stores of i32 values. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D48957 llvm-svn: 337168
* [mips] Add microMIPS case to the tests and regenerate assertions using ↵Simon Atanasyan2018-07-131-7/+114
| | | | | | update_llc_test_checks.py. NFC llvm-svn: 337004
* [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm testsJoel E. Denny2018-07-118-52/+52
| | | | | | | | | | | | | | | | | | | See https://reviews.llvm.org/D47106 for details. Reviewed By: probinson Differential Revision: https://reviews.llvm.org/D47171 This commit drops that patch's changes to: llvm/test/CodeGen/NVPTX/f16x2-instructions.ll llvm/test/CodeGen/NVPTX/param-load-store.ll For some reason, the dos line endings there prevent me from commiting via the monorepo. A follow-up commit (not via the monorepo) will finish the patch. llvm-svn: 336843
* [mips] Fix atomic operations at O0, v3Aleksandar Beserminji2018-07-054-428/+9037
| | | | | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the stores can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This version addresses issues with the initial implementation and covers all atomic operations. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Patch By: Simon Dardis Differential Revision: https://reviews.llvm.org/D31287 llvm-svn: 336328
* [mips] Warn when crc, ginv, virt flags are used with too old revisionVladimir Stefanovic2018-07-041-0/+45
| | | | | | | | | CRC and GINV ASE require revision 6, Virtualization requires revision 5. Print a warning when revision is older than required. Differential Revision: https://reviews.llvm.org/D48843 llvm-svn: 336296
* [MIPS GlobalISel] Lower arguments using stackPetar Jovanovic2018-07-031-0/+33
| | | | | | | | | | | Lower more than 4 arguments using stack. This patch targets MIPS32. It supports only functions with arguments of type i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D47934 llvm-svn: 336185
* [Mips][FastISel] Do not duplicate condition while lowering branchesPetar Jovanovic2018-07-021-0/+28
| | | | | | | | | | | | | | | | This change fixes the issue that arises when we duplicate condition from the predecessor block. If the condition's arguments are not considered alive across the blocks, fast regalloc gets confused and starts generating reloads from the slots that have never been spilled to. This change also leads to smaller code given that, unlike on architectures with condition codes, on Mips we can branch directly on register value, thus we gain nothing by duplication. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D48642 llvm-svn: 336084
* [mips] Support shrink-wrappingPetar Jovanovic2018-06-293-2/+394
| | | | | | | | | | Except for -O0, it's enabled by default. Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D47947 llvm-svn: 335989
* [mips] Add microMIPS specific addressing patterns.Simon Dardis2018-06-202-0/+74
| | | | | | | | | | | | | These are identical but use microMIPS instructions instead of MIPS instructions. Also, flatten the 'let AdditionalPredicates = [InMicroMips]' by using the ISA_MICROMIPS adjective. Add tests for constant materialization. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48275 llvm-svn: 335185
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