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* [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFCSimon Atanasyan2019-07-091-6/+12
| | | | | | | Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`. llvm-svn: 365507
* [mips] Correct label prefixes for N32 and N64.Daniel Sanders2016-07-191-18/+18
| | | | | | | | | | | | | | | | | Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
* [mips] Use --check-prefixes where appropriate. NFC.Daniel Sanders2016-06-241-6/+6
| | | | llvm-svn: 273669
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-6/+6
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [mips] Generate code for insert/extract operations when using the N64 ABI ↵Daniel Sanders2015-05-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-051-19/+55
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [mips][msa] Rename main check prefix to 'ALL' in basic operations tests. NFCDaniel Sanders2015-04-301-109/+109
| | | | | | | | | | | | | | | | Summary: The majority of the checks are subtarget independent. The few that aren't will be corrected shortly. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9340 llvm-svn: 236220
* [mips][msa] Use CHECK-LABEL where missing, and remove checks matching the ↵Daniel Sanders2015-04-301-15/+0
| | | | | | | | | | | | | | | | .size directive. NFC. Summary: Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9339 llvm-svn: 236219
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-301-0/+52
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
* [mips][msa] Use CHECK-LABEL in basic_operations*.llDaniel Sanders2014-04-291-13/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D3536 llvm-svn: 207529
* [mips][msa] Fix element extraction where the index is variable.Daniel Sanders2014-04-291-0/+43
| | | | | | | | | | | | | | Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 llvm-svn: 207524
* [mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3.Daniel Sanders2014-03-041-0/+18
| | | | | | | | | | Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 llvm-svn: 202848
* [mips] Prevent %lo relocation being used on MSA loads and stores.Daniel Sanders2014-03-031-9/+18
| | | | | | | | | | | | | | | | | Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
* [mips][msa] Build all the tests in little and big endian modes and correct ↵Daniel Sanders2013-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 llvm-svn: 194806
* [mips][msa] Added support for build_vector for v4f32 and v2f64.Daniel Sanders2013-10-151-4/+39
| | | | llvm-svn: 192699
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-271-0/+34
| | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-271-0/+80
| | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
* [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal ↵Daniel Sanders2013-09-271-1/+1
| | | | | | error when using it in FR=0 mode. llvm-svn: 191498
* [mips][msa] Implemented build_vector using ldi, fill, and custom ↵Daniel Sanders2013-09-231-0/+57
SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
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