summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/Mips/msa/arithmetic.ll
Commit message (Collapse)AuthorAgeFilesLines
* [MIPS] For vectors, select `add %x, C` as `sub %x, -C` if it results in ↵Roman Lebedev2019-09-181-8/+5
| | | | | | | | | | | | | | | | | | | | | | | inline immediate Summary: As discussed in https://reviews.llvm.org/D62341#1515637, for MIPS `add %x, -1` isn't optimal. Unlike X86 there are no fastpaths to matearialize such `-1`/`1` vector constants, and `sub %x, 1` results in better codegen, so undo canonicalization Reviewers: atanasyan, Petar.Avramovic, RKSimon Reviewed By: atanasyan Subscribers: sdardis, arichardson, hiraditya, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66805 llvm-svn: 372254
* [CodeGen][MIPS][NFC] Some standalone tests for D66805 "or vectors, select ↵Roman Lebedev2019-09-181-0/+67
| | | | | | `add %x, C` as `sub %x, -C` if it results in inline immediate" llvm-svn: 372253
* [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFCSimon Atanasyan2019-07-091-2/+2
| | | | | | | Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`. llvm-svn: 365507
* [NFC][Mips] Autogenerate msa/arithmetic.ll testRoman Lebedev2019-05-231-366/+323
| | | | | | Being affected by (sub %x, C) -> add %X, (sub 0, C) 'for vectors' patch. llvm-svn: 361522
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-88/+88
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* [mips][msa] Build all the tests in little and big endian modes and correct ↵Daniel Sanders2013-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 llvm-svn: 194806
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-111-0/+160
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 192438
* [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not ↵Daniel Sanders2013-10-011-0/+128
| | | | | | intrinsics) llvm-svn: 191737
* [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal ↵Daniel Sanders2013-09-271-1/+1
| | | | | | error when using it in FR=0 mode. llvm-svn: 191498
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-241-4/+8
| | | | | | (i.e. not intrinsics) llvm-svn: 191291
* [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+113
| | | | | | not intrinsics) llvm-svn: 191203
* [mips][msa] Added test cases that were supposed to be part of r190507, ↵Daniel Sanders2013-09-111-0/+320
r190509, r190512, and r190518. llvm-svn: 190522
OpenPOWER on IntegriCloud