| Commit message (Expand) | Author | Age | Files | Lines |
* | [MIPS] For vectors, select `add %x, C` as `sub %x, -C` if it results in inlin... | Roman Lebedev | 2019-09-18 | 1 | -8/+5 |
* | [CodeGen][MIPS][NFC] Some standalone tests for D66805 "or vectors, select `ad... | Roman Lebedev | 2019-09-18 | 1 | -0/+67 |
* | [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC | Simon Atanasyan | 2019-07-09 | 1 | -2/+2 |
* | [NFC][Mips] Autogenerate msa/arithmetic.ll test | Roman Lebedev | 2019-05-23 | 1 | -366/+323 |
* | [opaque pointer type] Add textual IR support for explicit type parameter to l... | David Blaikie | 2015-02-27 | 1 | -88/+88 |
* | [mips][msa] Build all the tests in little and big endian modes and correct an... | Daniel Sanders | 2013-11-15 | 1 | -0/+1 |
* | [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from no... | Daniel Sanders | 2013-10-11 | 1 | -0/+160 |
* | [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intr... | Daniel Sanders | 2013-10-01 | 1 | -0/+128 |
* | [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal e... | Daniel Sanders | 2013-09-27 | 1 | -1/+1 |
* | [mips][msa] Added support for matching max, maxi, min, mini from normal IR (i... | Daniel Sanders | 2013-09-24 | 1 | -4/+8 |
* | [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. ... | Daniel Sanders | 2013-09-23 | 1 | -0/+113 |
* | [mips][msa] Added test cases that were supposed to be part of r190507, r19050... | Daniel Sanders | 2013-09-11 | 1 | -0/+320 |