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path: root/llvm/test/CodeGen/MIR
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* [MachineVerifier] Add check that tied physregs aren't different.Mikael Holmen2017-07-061-0/+22
* AMDGPU: Add operand target flags serializationMatt Arsenault2017-07-021-0/+29
* Remove redundant copy in recurrencesTaewook Oh2017-06-291-1/+2
* llc: Add ability to parse mir from stdinMatthias Braun2017-06-061-0/+20
* MIRPrinter: Avoid assert() when printing empty INLINEASM strings.Matthias Braun2017-06-061-0/+12
* Vivek Pandya2017-06-0613-33/+46
* CodeGen: Refactor MIR parsingMatthias Braun2017-06-066-15/+22
* [RABasic] Properly initialize the passQuentin Colombet2017-06-021-0/+1
* TargetMachine: Indicate whether machine verifier passes.Matthias Braun2017-05-311-2/+2
* Revert "[IfConversion] Keep the CFG updated incrementally in IfConvertTriangle"Tobias Grosser2017-05-291-24/+0
* Move machine-cse-physreg.mir to test/CodeGen/ThumbKrzysztof Parzyszek2017-05-241-35/+0
* MachineCSE: Respect interblock physreg livenessMikael Holmen2017-05-241-0/+35
* [IfConversion] Keep the CFG updated incrementally in IfConvertTriangleMikael Holmen2017-05-121-0/+24
* [IfConversion] Add missing check in IfConversion/canFallThroughToMikael Holmen2017-05-101-0/+64
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-1/+1
* Add missing target triple to testMatthias Braun2017-05-051-1/+1
* MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun2017-05-054-29/+79
* MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFCMatthias Braun2017-05-011-1/+0
* MIR: Allow parsing of empty machine functionsJustin Bogner2017-04-118-41/+17
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-031-2/+2
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-215-14/+14
* [MIR] Test assumes x64 windows calling convention upon printing/parsing MIR o...Oren Ben Simhon2017-03-191-2/+2
* [MIR] Add triple to test that assumes it runs on windows.Benjamin Kramer2017-03-191-1/+1
* Moving the test to x86 because other architectures do not suport regcall call...Oren Ben Simhon2017-03-191-0/+0
* [MIR] Support Customed Register Mask and CSRsOren Ben Simhon2017-03-192-109/+30
* MIRTests: Remove unnecessary 2>&1 redirectionMatthias Braun2017-02-224-4/+4
* AMDGPU: Remove dead declarations from MIR testsMatt Arsenault2017-02-213-48/+5
* MIR: parse & print the atomic parts of a MachineMemOperand.Tim Northover2017-02-132-1/+31
* [MIRParser] Allow generic register specification on operand.Ahmed Bougacha2017-01-201-0/+3
* MIRParser: Allow regclass specification on operandMatthias Braun2017-01-184-0/+71
* [AArch64] Fold some filled/spilled subreg COPYsGeoff Berry2017-01-051-0/+82
* CodeGen: Assert that liveness is up to date when reading block live-ins.Matthias Braun2017-01-052-4/+8
* [GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet2016-12-222-2/+2
* [MIRParser] Fix a typo in comment and error message.Quentin Colombet2016-12-221-2/+2
* [MIRParser] Non-generic virtual register may have a type.Quentin Colombet2016-12-221-14/+0
* Move test to correct directoryMatthias Braun2016-12-171-157/+0
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-0/+709
* Add README describing the intention of test/CodeGen/MIRMatthias Braun2016-12-091-0/+7
* Move .mir tests to appropriate directoriesMatthias Braun2016-12-0923-3379/+0
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-052-1/+64
* AMDGPU: Move mir tests into mir test directoryMatt Arsenault2016-11-305-0/+647
* AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak2016-11-252-4/+177
* Revert "AMDGPU: Implement SGPR spilling with scalar stores"Marek Olsak2016-11-251-173/+0
* Revert "AMDGPU: Make m0 unallocatable"Marek Olsak2016-11-251-4/+4
* AMDGPU: Make m0 unallocatableMatt Arsenault2016-11-241-4/+4
* [AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.Geoff Berry2016-11-211-0/+27
* [MIRPrinter] XFAIL test for powerpcGeoff Berry2016-11-181-0/+2
* [MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry2016-11-184-5/+31
* MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard2016-11-151-2/+3
* RegAllocGreedy: Properly initialize this pass, so that -run-pass will workTom Stellard2016-11-141-0/+11
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