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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-24 00:26:40 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-24 00:26:40 +0000 |
| commit | 9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6 (patch) | |
| tree | b163ccaf77708f0e9a1e3082c207e49e2d8b6d7b /llvm/test/CodeGen/MIR | |
| parent | 8812f28f47a74d32bdd14181ebfe906cbfcd7346 (diff) | |
| download | bcm5719-llvm-9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6.tar.gz bcm5719-llvm-9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6.zip | |
AMDGPU: Make m0 unallocatable
m0 may need to be written for spill code, so
we don't want general code uses relying on the
value stored in it.
This introduces a few code quality regressions where copies
from m0 are not coalesced into copies of a copy of m0.
llvm-svn: 287841
Diffstat (limited to 'llvm/test/CodeGen/MIR')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir b/llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir index 016a6e6fd06..0c08deb13a8 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir @@ -6,14 +6,14 @@ name: phi_visit_order tracksRegLiveness: true registers: - - { id: 0, class: sreg_32 } + - { id: 0, class: sreg_32_xm0 } - { id: 1, class: sreg_64 } - - { id: 2, class: sreg_32 } + - { id: 2, class: sreg_32_xm0 } - { id: 7, class: vgpr_32 } - - { id: 8, class: sreg_32 } + - { id: 8, class: sreg_32_xm0 } - { id: 9, class: vgpr_32 } - { id: 10, class: sreg_64 } - - { id: 11, class: sreg_32 } + - { id: 11, class: sreg_32_xm0 } body: | ; GCN-LABEL: name: phi_visit_order |
