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path: root/llvm/test/CodeGen/MIR/Mips
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* [MIParser] Set RegClassOrRegBank during instruction parsingPetar Avramovic2019-10-221-9/+7
* [MIPS GlobalISel] Select MSA vector generic and builtin addPetar Avramovic2019-10-222-0/+68
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-312-52/+52
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-102-5/+5
* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-261-6/+6
* llc: Add support for -run-pass noneMatthias Braun2016-07-162-2/+2
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-131-1/+1
* [mips][mips16] Fix machine verifier errors about incorrect register classes o...Daniel Sanders2016-06-161-6/+6
* When printing MIR, output to errs() rather than outs().Justin Lebar2016-02-191-1/+1
* [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.Daniel Sanders2015-10-152-2/+2
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-202-6/+47
* MIR Serialization: Serialize the external symbol call entry pseudo sourceAlex Lorenz2015-08-141-0/+55
* MIR Serialization: Serialize the global value call entry pseudo source values.Alex Lorenz2015-08-142-0/+49
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