summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/CellSPU
Commit message (Collapse)AuthorAgeFilesLines
* fix visitShift to properly zero extend the shift amount if the provided operandChris Lattner2011-02-131-1/+1
| | | | | | | is narrower than the shift register. Doing an anyext provides undefined bits in the top part of the register. llvm-svn: 125457
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-201-0/+21
| | | | llvm-svn: 123912
* Don't crash SPU BE with memory accesses with big alignmnet.Kalle Raiskila2011-01-171-0/+9
| | | | llvm-svn: 123620
* Don't feed 19 bit immediates to ILA.Kalle Raiskila2010-12-171-2/+13
| | | | | | Patch (slightly modified) by Visa Putkinen. llvm-svn: 122052
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-061-24/+19
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. llvm-svn: 121059
* Handle lshr for i128 correctly on SPU also when Kalle Raiskila2010-11-291-2/+14
| | | | | | shiftamount > 7. llvm-svn: 120288
* Enable PostRA scheduling for SPU. Kalle Raiskila2010-11-292-4/+4
| | | | | | | This speeds up selected test cases with up to 5% - no slowdowns observed. llvm-svn: 120286
* Allow for 'fcmp ogt' in SPU.Kalle Raiskila2010-11-241-6/+19
| | | | | | Fix by Visa Putkinen! llvm-svn: 120090
* Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila2010-11-231-0/+22
| | | | | | shifts. llvm-svn: 120022
* Fix a bug with extractelement on SPU.Kalle Raiskila2010-11-221-1/+13
| | | | | | | In the attached testcase, the element was never extracted (missing rotate). llvm-svn: 119973
* Fix memory access lowering on SPU, addingKalle Raiskila2010-11-123-1/+26
| | | | | | | | | | | | support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. llvm-svn: 118889
* Change v64 datalayout in SPU.Kalle Raiskila2010-10-262-2/+15
| | | | | | | | | | | | | | The SPU ABI does not mention v64, and all examples in C suggest v128 are treated similarily to arrays, we use array alignment for v64 too. This makes the alignment of e.g. [2 x <2 x i32>] behave "intuitively" and similar to as if the elements were e.g. i32s. This also makes an "unaligned store" test to be aligned, with different (but functionally equivalent) code generated. llvm-svn: 117360
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-0/+3
| | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. llvm-svn: 116701
* Zap some redundant 'ori $?, $?, 0' from SPU.Kalle Raiskila2010-10-011-0/+1
| | | | | | | Also remove some code that died in the process. One now non-existant ori is checked for. llvm-svn: 115306
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-161-3/+2
| | | | | | | | | | | | | This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. llvm-svn: 114074
* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-081-0/+26
| | | | | | Some cases of lowering to rotate were miscompiled. llvm-svn: 113355
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-291-0/+8
| | | | | | The IDX was treated as byte index, not element index. llvm-svn: 112422
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-241-2/+24
| | | | | | llc used to assert on the added testcase. llvm-svn: 111911
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-181-0/+15
| | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. llvm-svn: 111361
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-183-10/+10
| | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. llvm-svn: 111360
* Change SPU C calling convention to match that described in Kalle Raiskila2010-08-181-0/+33
| | | | | | | | "SPU Application Binary Interface Specification, v1.9" by IBM. Specifically: use r3-r74 to pass parameters and the return value. llvm-svn: 111358
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-092-3/+15
| | | | llvm-svn: 110576
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-042-0/+25
| | | | | | store for "half vectors" llvm-svn: 110198
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-021-0/+10
| | | | llvm-svn: 110038
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-021-0/+35
| | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-021-0/+57
| | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. llvm-svn: 110035
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-161-1/+1
| | | | | | TII::isMoveInstr is going tobe completely removed. llvm-svn: 108507
* Fix some tests that didn't test anything.Benjamin Kramer2010-06-261-1/+1
| | | | llvm-svn: 106954
* Add the check to the testcase of r106419.Kalle Raiskila2010-06-211-0/+3
| | | | llvm-svn: 106421
* Mark the SPU 'lr' instruction to never have side effects. Kalle Raiskila2010-06-214-13/+18
| | | | | | | | | This allows the fast regiser allocator to remove redundant register moves. Update a set of tests that depend on the register allocator to be linear scan. llvm-svn: 106420
* Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.Kalle Raiskila2010-06-211-1/+6
| | | | llvm-svn: 106419
* Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithmKalle Raiskila2010-06-211-0/+10
| | | | | | | used to choke llc with the attached test. llvm-svn: 106411
* Fix SPU to cope with vector insertelement to an undef position.Kalle Raiskila2010-06-091-2/+13
| | | | | | We default to inserting to lane 0. llvm-svn: 105722
* Handle loading from/storing to undef pointers on SPU by inserting a Kalle Raiskila2010-06-091-0/+5
| | | | | | random load/store, rather than crashing llc. llvm-svn: 105710
* Fix handling of 'load' nodes.Kalle Raiskila2010-06-011-0/+13
| | | | llvm-svn: 105269
* Make SPU backend not assert on jump tables.Kalle Raiskila2010-05-111-0/+21
| | | | llvm-svn: 103466
* Fix encoding of 'sf' and 'sfh' instructions.Kalle Raiskila2010-05-101-0/+26
| | | | llvm-svn: 103399
* "on the rare occasion the SPU BE produces illegal assembly - it tries to ↵Chris Lattner2010-05-041-0/+13
| | | | | | | | emit an add instruction of the form 'a reg, reg, imm'." Patch by Kalle Raiskila! llvm-svn: 103021
* teach cellspu how to return i8 and i16 from calls,Chris Lattner2010-04-201-0/+8
| | | | | | patch by Kalle Raiskila! llvm-svn: 101875
* Make sure this test tests something.Benjamin Kramer2010-04-091-3/+7
| | | | llvm-svn: 100879
* "On SPU, variables in the .bss section that are allocated with the .lcomm ↵Chris Lattner2010-04-091-0/+2
| | | | | | | | | | directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment. this patch disables .lcomm in favour of '.local .comm' Patch by Kalle Raisklia! llvm-svn: 100875
* Split big test into multiple directories to cater toDale Johannesen2010-04-071-0/+33
| | | | | | those who don't build all targets. llvm-svn: 100688
* From Kalle Raiskila:Chris Lattner2010-03-291-0/+17
| | | | | | | | "the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions: -in vararg handling, registers are marked to be live, to not confuse the register scavenger -function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack." llvm-svn: 99819
* fix bss section printing for cell, patch by Kalle Raiskila!Chris Lattner2010-03-051-0/+5
| | | | llvm-svn: 97814
* don't let asm-verbose break the check-next lines in these tests.Chris Lattner2010-01-191-2/+2
| | | | llvm-svn: 93869
* Teach dag combine to fold the following transformation more aggressively:Evan Cheng2010-01-061-1/+0
| | | | | | | | | | (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. llvm-svn: 92849
* Delete useless trailing semicolons.Dan Gohman2010-01-052-2/+2
| | | | llvm-svn: 92740
* Revert this dag combine change:Evan Cheng2009-12-171-4/+4
| | | | | | | | Fold (zext (and x, cst)) -> (and (zext x), cst) DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping. llvm-svn: 91574
* Fold (zext (and x, cst)) -> (and (zext x), cst).Evan Cheng2009-12-151-4/+4
| | | | llvm-svn: 91380
* Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng2009-12-091-3/+3
| | | | | | isl lowering code. llvm-svn: 90925
OpenPOWER on IntegriCloud