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* [AVR] Fix a typo in the testsDylan McKay2017-07-161-2/+2
| | | | llvm-svn: 308148
* [AVR] Fix indirect calls to function pointersDylan McKay2017-07-131-0/+15
| | | | | | Patch by Carl Peto. llvm-svn: 307888
* [AVR] Use the generic branch relaxerDylan McKay2017-07-114-7/+104
| | | | llvm-svn: 307617
* [AVR] Fix test errors due to tied operands not matchingDylan McKay2017-07-095-7/+7
| | | | | | Broken due to r307259. llvm-svn: 307503
* Revert "[AVR] Add the branch selection pass from the GitHub repository"Dylan McKay2017-07-053-7/+7
| | | | | | This reverts commit 602ef067c1d58ecb425d061f35f2bc4c7e92f4f3. llvm-svn: 307111
* [AVR] Add the branch selection pass from the GitHub repositoryDylan McKay2017-07-053-7/+7
| | | | | | | We should rewrite this using the generic branch relaxation pass, but for the moment having this pass is better than hitting an assertion error. llvm-svn: 307109
* [AVR] Fix bug which caused assertion errors for some FRMIDX instructionsDylan McKay2017-07-041-0/+33
| | | | | | | | | | | | | Previously, if a basic block ended with a FRMIDX instruction, we would end up doing something like this. *std::next(MBB.end()) Which would hit an error: "Assertion `!NodePtr->isKnownSentinel()' failed." llvm-svn: 307057
* [AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo ErdiDylan McKay2017-05-311-2/+2
| | | | | | | When generating code for a shift loop, check the shift amount against the literal value 0, not R0 llvm-svn: 304284
* [AVR] When lowering Select8/Select16, put newly generated MBBs in the same spotDylan McKay2017-05-131-0/+35
| | | | | | | | | | Contributed by Dr. Gergő Érdi. Fixes a bug. Raised from (https://github.com/avr-rust/rust/issues/49). llvm-svn: 302973
* [AVR] Reserve the Y register in all functionsDylan McKay2017-05-033-4/+3
| | | | llvm-svn: 302017
* [AVR] Save/restore the frame pointer for all functionsDylan McKay2017-05-023-19/+19
| | | | | | | A recent commit I made made it so that we only did this for signal or interrupt handlers. This broke normal functions. llvm-svn: 301893
* [AVR] Implement non-constant bit rotationsDylan McKay2017-05-011-0/+55
| | | | | | This lets us do bit rotations of variable amount. llvm-svn: 301794
* [AVR] Support the LDWRdPtr instruction with the same Src+Dst registerDylan McKay2017-04-253-35/+64
| | | | llvm-svn: 301313
* [AVR] Remove the 'multibyte' asm testDylan McKay2017-04-191-135/+0
| | | | | | It tests registers which are not actually used on AVR. llvm-svn: 300684
* [AVR] Fix the test suiteDylan McKay2017-04-194-35/+40
| | | | | | | | | | | | A bunch of tests failed because memory operations have been reordered. I am unsure which commit changed this behaviour as the AVR build was failing at that point with an unrelated error. This commit just reoders some of the CHECK lines in some tests to suit current llc output. llvm-svn: 300682
* [AVR] Disable integrated assembler for a few testsDylan McKay2017-02-223-3/+3
| | | | | | Fixes the build. llvm-svn: 295895
* MIRTests: Remove unnecessary 2>&1 redirectionMatthias Braun2017-02-2238-38/+38
| | | | | | | llc mir output goes to stdout nowadays, so the 2>&1 is not necessary anymore for most tests. llvm-svn: 295859
* [AVR] Implement stacksave/stackrestore by expanding (PR31342)Dylan McKay2017-02-051-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Authored by Florian Zeitz. This implements the missing stacksave/stackrestore intrinsics via expansion. Output of `llc -O0 -march=avr ~/devel/llvm/test/CodeGen/Generic/stacksave-restore.ll` for sanity checking (comments mine): ``` .text .file ".../llvm/test/CodeGen/Generic/stacksave-restore.ll" .globl test .p2align 1 .type test,@function test: ; @test ; BB#0: push r28 push r29 in r28, 61 in r29, 62 sbiw r28, 4 in r0, 63 cli out 62, r29 out 63, r0 out 61, r28 in r18, 61 in r19, 62 mov r20, r22 mov r21, r23 in r30, 61 in r31, 62 lsl r22 rol r23 lsl r22 rol r23 in r26, 61 in r27, 62 sub r26, r22 sbc r27, r23 andi r26, 252 in r0, 63 cli out 62, r27 out 63, r0 out 61, r26 in r0, 63 cli out 62, r31 out 63, r0 out 61, r30 in r30, 61 in r31, 62 sub r30, r22 sbc r31, r23 andi r30, 252 in r0, 63 cli out 62, r31 out 63, r0 out 61, r30 std Y+3, r24 ; 2-byte Folded Spill std Y+4, r25 ; 2-byte Folded Spill mov r24, r26 mov r25, r27 in r0, 63 cli out 62, r19 out 63, r0 out 61, r18 std Y+1, r20 ; 2-byte Folded Spill std Y+2, r21 ; 2-byte Folded Spill adiw r28, 4 in r0, 63 cli out 62, r29 out 63, r0 out 61, r28 pop r29 pop r28 ret .Lfunc_end0: .size test, .Lfunc_end0-test ``` Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29553 llvm-svn: 294146
* [AVR] Marm MIR test functions as tracking liveness informationDylan McKay2017-02-053-2/+5
| | | | | | This fixes an assertion error that broke three tests. llvm-svn: 294140
* [AVR] Fix a bug where asm operands are printed twiceDylan McKay2017-02-051-0/+8
| | | | | | | We would unconditionally call printOperand, even if PrintAsmOperand already printed the immediate. llvm-svn: 294121
* [AVR] Implement TargetLoweing::getRegisterByNameDylan McKay2017-01-071-0/+17
| | | | | | | This allows the use of the 'read_register' intrinsics used by clang's named register globals features. llvm-svn: 291375
* [AVR] Optimize 16-bit ANDs with '1'Dylan McKay2016-12-312-1/+53
| | | | | | | | | | | | Summary: Fixes PR 31345 Reviewers: dylanmckay Subscribers: fhahn, llvm-commits Differential Revision: https://reviews.llvm.org/D28186 llvm-svn: 290778
* [AVR] Optimize 16-bit ORs with '0'Dylan McKay2016-12-302-4/+37
| | | | | | | | | | | | | | Summary: Fixes PR 31344 Authored by Anmol P. Paralkar Reviewers: dylanmckay Subscribers: fhahn, llvm-commits Differential Revision: https://reviews.llvm.org/D28121 llvm-svn: 290732
* [CodeGenPrep] Skip merging empty case blocksJun Bum Lim2016-12-161-1/+1
| | | | | | | | | | | | | | This is recommit of r287553 after fixing the invalid loop info after eliminating an empty block and unit test failures in AVR and WebAssembly : Summary: Merging an empty case block into the header block of switch could cause ISel to add COPY instructions in the header of switch, instead of the case block, if the case block is used as an incoming block of a PHI. This could potentially increase dynamic instructions, especially when the switch is in a loop. I added a test case which was reduced from the benchmark I was targetting. Reviewers: t.p.northover, mcrosier, manmanren, wmi, joerg, davidxl Subscribers: joerg, qcolombet, danielcdh, hfinkel, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22696 llvm-svn: 289988
* [AVR] Add a test for 64-bit left shiftsDylan McKay2016-12-161-0/+8
| | | | llvm-svn: 289936
* [AVR] Support floats in the instrumention passDylan McKay2016-12-151-4/+21
| | | | | | This also refactors some common code into the 'GetTypeName' method. llvm-svn: 289803
* [AVR] Add a function instrumentation passDylan McKay2016-12-141-0/+45
| | | | | | This will be used for an on-chip test suite. llvm-svn: 289641
* [AVR] Add an 'relax memory operation' passDylan McKay2016-12-131-0/+31
| | | | | | | | | | | | | | | | | | | | | | Summary: This pass will be used to relax instructions which use out of bounds memory accesses to equivalent operations that can work with the addresses. The pass currently implements relaxation for the STDWPtrQRr instruction. Without this pass, an assertion error would be hit in the pseudo expansion pass. In the future, we will need to add more instructions to this pass. We can do that on a case-by-case basic. Reviewers: arsenm, kparzysz Subscribers: wdng, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D27650 llvm-svn: 289517
* [AVR] Add calling convention CodeGen testsDylan McKay2016-12-113-0/+167
| | | | | | This adds CodeGen tests for the AVR C calling convention. llvm-svn: 289369
* [AVR] Add a test to validate a simple 'blinking led' programDylan McKay2016-12-111-0/+125
| | | | llvm-svn: 289362
* [AVR] Fix and clean up the inline assembly testsDylan McKay2016-12-104-337/+338
| | | | | | | | | | There was a bug where we would hit an assertion if 'Q' was used as a constraint. I also removed hardcoded register names to prefer regexes so the tests don't break when the register allocator changes. llvm-svn: 289325
* [AVR] Explicitly set the target in all CodeGen testsDylan McKay2016-12-104-4/+4
| | | | | | This seems to have caused failures on the buildbot. llvm-svn: 289324
* [AVR] Use the register scavenger when expanding 'LDDW' instructionsDylan McKay2016-12-101-12/+13
| | | | | | | | | | | | Summary: This gets rid of the hardcoded 'r0' that was used previously. Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27567 llvm-svn: 289322
* [AVR] Support stores to undefined pointersDylan McKay2016-12-101-0/+13
| | | | | | This would previously trigger an assertion error in AVRISelDAGToDAG. llvm-svn: 289321
* [AVR] Remove a set of redundant testsDylan McKay2016-12-094-88/+0
| | | | | | This fixes the build. llvm-svn: 289201
* [AVR] Add tests for a large number of pseudo instructionsDylan McKay2016-12-0927-4/+560
| | | | | | This adds MIR tests for 24 pseudo instructions. llvm-svn: 289191
* [AVR] Add MIR tests for pseudo instruction expansionsDylan McKay2016-12-0813-0/+308
| | | | | | This adds tests for 13 pseudo instruction expansions. llvm-svn: 289039
* [AVR] Add MIR tests for a few pseudo instructionsDylan McKay2016-12-083-0/+72
| | | | llvm-svn: 289031
* [AVR] Expand 'SELECT_CC' nodes whereever possibleDylan McKay2016-12-071-2/+0
| | | | llvm-svn: 288905
* [AVR] Move a pseudo expansion test into a folderDylan McKay2016-12-071-0/+0
| | | | llvm-svn: 288899
* [AVR] Allow loading from stack slots where src and dest registers are identicalDylan McKay2016-12-072-56/+33
| | | | | | Fixes PR 31256 llvm-svn: 288897
* [AVR] Remove 'XFAIL' from a CodeGen testDylan McKay2016-12-041-1/+0
| | | | | | This seems to be fixed as of r288052. llvm-svn: 288618
* Un-XFAIL an AVR CodeGen testDylan McKay2016-11-261-1/+0
| | | | llvm-svn: 287958
* [AVR] Mark the 'select-must-add-unconditional-jump' test as 'XFAIL'Dylan McKay2016-11-241-0/+1
| | | | llvm-svn: 287871
* [AVR] Remove some accidentally-commited code that broke the botsDylan McKay2016-11-171-24/+0
| | | | | | | | | This is a remnant of an on-chip unit testing tool that has since been moved out-of-tree. It was accidentally committed in r287162. llvm-svn: 287180
* [AVR] Fix basic block naming in ctlz and cttz testsDylan McKay2016-11-162-4/+4
| | | | | | The branch selector would change the names. llvm-svn: 287174
* [AVR] Add tests for counting leading/trailing zerosDylan McKay2016-11-162-0/+88
| | | | | | This adds two test files that verify the 'cttz' and 'ctlz' operations. llvm-svn: 287172
* [AVR] Add the pseudo instruction expansion passDylan McKay2016-11-1633-0/+2979
| | | | | | | | | | | | | | | | | | Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
* [AVR] Add a selection of CodeGen testsDylan McKay2016-11-0919-0/+556
| | | | | | | | | | | | Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
* [RegAllocGreedy] Attempt to split unspillable live intervalsDylan McKay2016-10-111-0/+78
| | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, when allocating unspillable live ranges, we would never attempt to split. We would always bail out and try last ditch graph recoloring. This patch changes this by attempting to split all live intervals before performing recoloring. This fixes LLVM bug PR14879. I can't add test cases for any backends other than AVR because none of them have small enough register classes to trigger the bug. Reviewers: qcolombet Subscribers: MatzeB Differential Revision: https://reviews.llvm.org/D25070 llvm-svn: 283838
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