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authorDylan McKay <me@dylanmckay.io>2017-05-01 09:48:55 +0000
committerDylan McKay <me@dylanmckay.io>2017-05-01 09:48:55 +0000
commit59e7fe3da8092e7dfb13376b959418bb507eaf87 (patch)
tree7ecf9a6b8d7e46e71aef2aeff38e869e13781590 /llvm/test/CodeGen/AVR
parent4064dc76c52d9eefcf8026f2c8b91d67f470e86d (diff)
downloadbcm5719-llvm-59e7fe3da8092e7dfb13376b959418bb507eaf87.tar.gz
bcm5719-llvm-59e7fe3da8092e7dfb13376b959418bb507eaf87.zip
[AVR] Implement non-constant bit rotations
This lets us do bit rotations of variable amount. llvm-svn: 301794
Diffstat (limited to 'llvm/test/CodeGen/AVR')
-rw-r--r--llvm/test/CodeGen/AVR/rot.ll55
1 files changed, 55 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AVR/rot.ll b/llvm/test/CodeGen/AVR/rot.ll
new file mode 100644
index 00000000000..e43daf3e6aa
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/rot.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+; Bit rotation tests.
+
+; CHECK-LABEL: rol8:
+define i8 @rol8(i8 %val, i8 %amt) {
+ ; CHECK: andi r22, 7
+
+ ; CHECK-NEXT: cp r22, r0
+ ; CHECK-NEXT: breq LBB0_2
+
+; CHECK-NEXT: LBB0_1:
+ ; CHECK-NEXT: rol r24
+ ; CHECK-NEXT: subi r22, 1
+ ; CHECK-NEXT: brne LBB0_1
+
+; CHECK-NEXT:LBB0_2:
+ ; CHECK-NEXT: ret
+ %mod = urem i8 %amt, 8
+
+ %inv = sub i8 8, %mod
+ %parta = shl i8 %val, %mod
+ %partb = lshr i8 %val, %inv
+
+ %rotl = or i8 %parta, %partb
+
+ ret i8 %rotl
+}
+
+
+; CHECK-LABEL: ror8:
+define i8 @ror8(i8 %val, i8 %amt) {
+ ; CHECK: andi r22, 7
+
+ ; CHECK-NEXT: cp r22, r0
+ ; CHECK-NEXT: breq LBB1_2
+
+; CHECK-NEXT: LBB1_1:
+ ; CHECK-NEXT: ror r24
+ ; CHECK-NEXT: subi r22, 1
+ ; CHECK-NEXT: brne LBB1_1
+
+; CHECK-NEXT:LBB1_2:
+ ; CHECK-NEXT: ret
+ %mod = urem i8 %amt, 8
+
+ %inv = sub i8 8, %mod
+ %parta = lshr i8 %val, %mod
+ %partb = shl i8 %val, %inv
+
+ %rotr = or i8 %parta, %partb
+
+ ret i8 %rotr
+}
+
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