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| author | Matthias Braun <matze@braunis.de> | 2017-02-22 18:47:41 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2017-02-22 18:47:41 +0000 |
| commit | f1141285eb1f8bd857bb646ff54b2cacf75b28fc (patch) | |
| tree | 2de0f974188b19d650aeb8db6aee5b0865ada2b3 /llvm/test/CodeGen/AVR | |
| parent | 6eaed7aceb78f235b8e9e7690d3768937d4555a2 (diff) | |
| download | bcm5719-llvm-f1141285eb1f8bd857bb646ff54b2cacf75b28fc.tar.gz bcm5719-llvm-f1141285eb1f8bd857bb646ff54b2cacf75b28fc.zip | |
MIRTests: Remove unnecessary 2>&1 redirection
llc mir output goes to stdout nowadays, so the 2>&1 is not necessary
anymore for most tests.
llvm-svn: 295859
Diffstat (limited to 'llvm/test/CodeGen/AVR')
38 files changed, 38 insertions, 38 deletions
diff --git a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir index 475d5b39299..b1fc792d659 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit add with carry pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir index 2205febcc93..5743b153633 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit add pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir index 5af8db15951..bcea4e6dfe2 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit ANDO pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir index c9458e9ba5d..f6b060a5d73 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit AND pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir index 3e809564ca1..5253dcd87f1 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir index 282d601686a..58ff7af7cb3 100644 --- a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit COM pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir index 2081aa0b5ee..c0ab60e8929 100644 --- a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit CPCW pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir index 7e25e7fe227..c93c99151a4 100644 --- a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit CPW pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir index 8769c12cbb1..de53c2d077e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit EOR pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir index 47a9397fa6b..b56122a43ad 100644 --- a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir +++ b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # TODO: Write this test. # This instruction isn't expanded by the pseudo expansion passs, but diff --git a/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir b/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir index a801598fadd..1b2d7fa0f53 100644 --- a/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir +++ b/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir index 09d0b96164d..5ff2ef1742e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s +# RUN: llc -O0 %s -o - -march=avr | FileCheck %s # This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir index 7d3251adbda..831c75b38b1 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s +# RUN: llc -O0 %s -o - -march=avr | FileCheck %s # This test checks the expansion of the 16-bit 'LDDWRdYQ instruction diff --git a/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir index 23d16d9c569..f4788adf20b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDIWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir index aa4883634d7..b813923abcb 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDSWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir index aaf9f182f2b..6db615878b9 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir index f304cc220cb..eb65c6538d1 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir index 9153be0bf1c..50bad2a4c76 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir index 441939856ae..537944866e5 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir index f5ffb93f403..a1a513f4e36 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir index 92bc36769eb..d77a6ba8848 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit OR pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir index f7a377ec860..834c21cba8f 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit OR pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir index 85e9f5259a8..99abad1c31b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir b/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir index 6794742bf54..8bd7fe68727 100644 --- a/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir b/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir index 93920867030..ec94ecbf5bb 100644 --- a/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir index 9152c6d9126..644e6106ee7 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir index 9159906b76a..5cf5d33252c 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir index 069eb883dcc..0d10358c10e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir b/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir index ff2fdb9155e..9252997d489 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir index ccf852271ae..18f10180809 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit STSWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir index 0d0d9e909e4..d884d2121c2 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir index a436d9b109b..962776aa633 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir index f85f4f8a045..efed707bfe8 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit STSWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir index 95c68c0a122..c7d88d7ab3f 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir index 9892cf5b7f3..b12b0e5349e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir index 069eb883dcc..0d10358c10e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir b/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir index 52945e6cf84..8427a2bfb4e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir +++ b/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s +# RUN: llc -O0 %s -o - -march=avr | FileCheck %s # This test ensures that the pseudo expander can correctly handle the case # where we are expanding a 16-bit LDD instruction where the source and diff --git a/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir b/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir index b43c7750832..7421bd4c4e8 100644 --- a/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir +++ b/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s --- | target triple = "avr--" |
