bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)	Vedant Kumar	2018-05-01	1	-1/+1
*	ARM: handle post-indexed NEON ops where the offset isn't the access width.	Tim Northover	2017-04-20	1	-3/+14
*	SDag: fix how initial loads are formed when splitting vector ops.	Tim Northover	2017-01-25	1	-0/+10
*	ARM: Enable MachineScheduler and disable PostRAScheduler for swift.	Matthias Braun	2015-07-17	1	-2/+2
*	Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift."	Adam Nemet	2015-07-17	1	-2/+2
*	ARM: Enable MachineScheduler and disable PostRAScheduler for swift.	Matthias Braun	2015-07-17	1	-2/+2
*	[opaque pointer type] Add textual IR support for explicit type parameter to l...	David Blaikie	2015-02-27	1	-52/+52
*	[opaque pointer type] Add textual IR support for explicit type parameter to g...	David Blaikie	2015-02-27	1	-15/+15
*	[ARM] Re-re-apply VLD1/VST1 base-update combine.	Ahmed Bougacha	2015-02-19	1	-0/+253
*	Reverting VLD1/VST1 base-updating/post-incrementing combining	Renato Golin	2015-02-04	1	-253/+0
*	[ARM] Don't break alignment when combining base updates into load/stores.	Ahmed Bougacha	2014-12-23	1	-9/+50
*	Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."	Ahmed Bougacha	2014-12-13	1	-0/+212
*	Revert "[ARM] Combine base-updating/post-incrementing vector load/stores."	Renato Golin	2014-12-13	1	-184/+0
*	[ARM] Combine base-updating/post-incrementing vector load/stores.	Ahmed Bougacha	2014-12-10	1	-0/+184