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path: root/llvm/test/CodeGen/ARM/atomic-64bit.ll
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* ARM: Better codegen for 64-bit compares.Peter Collingbourne2016-03-211-96/+72
* ARM: sink atomic release barrier as far as possible into cmpxchg.Tim Northover2016-02-221-9/+9
* AArch64: use ldxp/stxp pair to implement 128-bit atomic loads.Tim Northover2015-12-021-0/+6
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-1/+1
* Add a new string member to the TargetOptions struct for the nameEric Christopher2014-12-181-1/+1
* Model ARM backend ABI selection after the front end code doing theEric Christopher2014-12-181-1/+1
* Atomics: make use of the "cmpxchg weak" instruction.Tim Northover2014-06-131-2/+3
* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-131-1/+2
* ARM & AArch64: make use of common cmpxchg idioms after expansionTim Northover2014-05-301-3/+3
* ARM big endian function argument passingChristian Pirker2014-05-081-45/+86
* ARM: expand atomic ldrex/strex loops in IRTim Northover2014-04-031-41/+114
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-111-1/+1
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-15/+1
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-221-1/+1
* Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f...Stephen Lin2013-07-141-13/+13
* Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging....Stephen Lin2013-07-131-13/+13
* ARM: relax the atomic release barrier to "dmb ishst" on SwiftTim Northover2013-07-031-50/+50
* Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")Tim Northover2013-07-011-50/+50
* ARM: relax the atomic release barrier to "dmb ishst"Tim Northover2013-07-011-50/+50
* Fix 64-bit atomic operations in Thumb mode.Tim Northover2013-01-291-0/+147
* Fixed the condition codes for the atomic64 min/umin code generation on ARM. I...Silviu Baranga2013-01-251-2/+2
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-291-0/+61
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-41/+41
* Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implemen...Eli Friedman2011-08-311-7/+37
* 64-bit atomic cmpxchg for ARM.Eli Friedman2011-08-311-0/+15
* Some minor cleanups for r138845.Eli Friedman2011-08-311-1/+1
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-311-0/+83
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