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* AMDGPU/GlobalISel: Basic legality for load/storeMatt Arsenault2018-03-172-0/+253
| | | | llvm-svn: 327772
* [AMDGPU] Supported ds_write_b128 generation.Farhana Aleen2018-03-166-17/+43
| | | | | | | | | | | | | | Summary: This is a follow-on patch of https://reviews.llvm.org/D44210 Author: FarhanaAleen Reviewed By: msearles Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D44319 llvm-svn: 327726
* [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP ↵Dmitry Preobrazhensky2018-03-161-43/+43
| | | | | | | | | | | opcodes See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751 Differential Revision: https://reviews.llvm.org/D44529 Reviewers: artem.tamazov, arsenm llvm-svn: 327723
* [AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate info in the case ↵Mark Searles2018-03-141-0/+26
| | | | | | | | of a single basic block loop. mergeInputScoreBrackets() does this for us; update it so that it processes the single bb's score bracket when processing the single bb's preds. It is, after all, a pred of itself, so it's score bracket is needed. Differential Revision: https://reviews.llvm.org/D44434 llvm-svn: 327583
* [CodeGen] Use MIR syntax for MachineMemOperand printingFrancis Visoiu Mistrih2018-03-141-1/+1
| | | | | | | | | | Get rid of the "; mem:" suffix and use the one we use in MIR: ":: (load 2)". rdar://38163529 Differential Revision: https://reviews.llvm.org/D42377 llvm-svn: 327580
* [AMDGPU] Fix lowering enqueue kernel when kernel has no nameYaxun Liu2018-03-121-9/+47
| | | | | | | | | | Since the enqueued kernels have internal linkage, their names may be dropped. In this case, give them unique names __amdgpu_enqueued_kernel or __amdgpu_enqueued_kernel.n where n is a sequential number starting from 1. Differential Revision: https://reviews.llvm.org/D44322 llvm-svn: 327291
* [AMDGPU][MC] Corrected GATHER4 opcodesDmitry Preobrazhensky2018-03-122-56/+0
| | | | | | | | | See bug 36252: https://bugs.llvm.org/show_bug.cgi?id=36252 Differential Revision: https://reviews.llvm.org/D43874 Reviewers: artem.tamazov, arsenm llvm-svn: 327278
* AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELTMatt Arsenault2018-03-124-0/+392
| | | | llvm-svn: 327269
* AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUESMatt Arsenault2018-03-122-1/+45
| | | | llvm-svn: 327268
* AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legalMatt Arsenault2018-03-122-0/+147
| | | | llvm-svn: 327267
* [AMDGPU] fix tests to be independent of FP undefSanjay Patel2018-03-103-43/+42
| | | | llvm-svn: 327211
* AMDGPU: Fix crash when constant folding with physreg operandMatt Arsenault2018-03-101-0/+27
| | | | llvm-svn: 327209
* [AMDGPU] Supported ds_read_b128 generation; Widened vector length for local ↵Farhana Aleen2018-03-096-0/+105
| | | | | | | | | | | | | | | | | | | | address-space. Summary: Starting from GCN 2nd generation, ISA supports ds_read_b128 on top of ds_read_b64. This patch supports ds_read_b128 instruction pattern and generation of this instruction. In the vectorizer, this patch also widen the vector length so that vectorizer generates 128 bit loads for local address-space which gets translated to ds_read_b128. Since the performance benefit is not clear; compiler generates ds_read_b128 under -amdgpu-ds128. Author: FarhanaAleen Reviewed By: rampitec, arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D44210 llvm-svn: 327153
* [AMDGPU] fix test to be independent of FP undefSanjay Patel2018-03-091-2/+2
| | | | llvm-svn: 327147
* [AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9Stanislav Mekhanoshin2018-03-091-58/+59
| | | | | | | | GFX9 should select opsel version. Differential Revision: https://reviews.llvm.org/D44279 llvm-svn: 327106
* [AMDGPU] fix test to survive more FP undef constant foldingSanjay Patel2018-03-081-5/+6
| | | | llvm-svn: 327066
* [AMDGPU] fix test to survive the most basic undef constant foldingSanjay Patel2018-03-081-1/+1
| | | | | | | This will likely need to be changed again for anything more than: fmul undef, undef -> undef llvm-svn: 327034
* [AMDGPU] Increased vector length for global/constant loads.Farhana Aleen2018-03-073-1/+71
| | | | | | | | | | | | | | | Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D44179 llvm-svn: 326910
* Revert "[AMDGPU] Widened vector length for global/constant address space."Farhana Aleen2018-03-073-71/+1
| | | | | | This reverts commit ce988cc100dc65e7c6c727aff31ceb99231cab03. llvm-svn: 326907
* [AMDGPU] Widened vector length for global/constant address space.Farhana Aleen2018-03-073-1/+71
| | | | llvm-svn: 326904
* [AMDGPU] Fix lowering OpenCL enqueue_kernelYaxun Liu2018-03-061-49/+44
| | | | | | | | | | One addrspacecast disappeared in clang emitted IR for block invoke function due to adoption of the new addr space mapping. Differential Revision: https://reviews.llvm.org/D43785 llvm-svn: 326806
* AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACTMatt Arsenault2018-03-051-0/+31
| | | | llvm-svn: 326715
* AMDGPU/GlobalISel: Make some G_EXTRACTs legalMatt Arsenault2018-03-051-0/+105
| | | | | | | As far as I can tell legalization of weird sizes for the output type isn't implemented. llvm-svn: 326714
* Pass Divergence Analysis data to Selection DAG to drive divergenceAlexander Timofeev2018-03-052-16/+59
| | | | | | | | dependent instruction selection. Differential revision: https://reviews.llvm.org/D35267 llvm-svn: 326703
* AMDGPU/GlobalISel: InstrMapping for G_ZEXTMatt Arsenault2018-03-021-0/+31
| | | | llvm-svn: 326589
* AMDGPU/GlobalISel: InstrMapping for G_TRUNCMatt Arsenault2018-03-021-0/+31
| | | | llvm-svn: 326588
* AMDGPU/GlobalISel: Define InstrMappings for G_FCMPMatt Arsenault2018-03-021-0/+69
| | | | | | Patch by Tom Stellard llvm-svn: 326587
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnumMatt Arsenault2018-03-021-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326586
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnumMatt Arsenault2018-03-021-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326567
* AMDGPU/GCN: Promote i16 ctpopJan Vesely2018-03-021-0/+334
| | | | | | | | | i16 capable ASICs do not support i16 operands for this instruction. Add tablegen pattern to merge chained i16 additions. Differential Revision: https://reviews.llvm.org/D43985 llvm-svn: 326535
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSIMatt Arsenault2018-03-021-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326534
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUIMatt Arsenault2018-03-021-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326533
* AMDGPU/GlobalISel: Define instruction mapping for G_FMULMatt Arsenault2018-03-021-0/+69
| | | | llvm-svn: 326532
* AMDGPU/GlobalISel: Define instruction mapping for G_FADDMatt Arsenault2018-03-021-0/+69
| | | | | | Patch by Tom Stellard llvm-svn: 326526
* AMDGPU/GlobalISel: Define instruction mapping for G_SHLMatt Arsenault2018-03-021-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326525
* AMDGPU/GlobalISel: Define instruction mapping for G_XORMatt Arsenault2018-03-021-0/+68
| | | | llvm-svn: 326524
* AMDGPU/GlobalISel: Define instruction mapping for G_ANDMatt Arsenault2018-03-021-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326523
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtzMatt Arsenault2018-03-011-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326490
* AMDGPU/GlobalISel: Define instruction mapping for G_ORMatt Arsenault2018-03-011-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326489
* AMDGPU/GlobalISel: Define instruction mapping for G_BITCASTMatt Arsenault2018-03-011-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326482
* AMDGPU/GlobalISel: Mark i32->i64 zext as legalMatt Arsenault2018-03-011-0/+14
| | | | llvm-svn: 326481
* AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.comprMatt Arsenault2018-03-011-0/+67
| | | | | | Patch by Tom Stellard llvm-svn: 326479
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.expMatt Arsenault2018-03-011-0/+77
| | | | | | Patch by Tom Stellard llvm-svn: 326477
* AMDGPU/GlobalISel: Define InstrMappings for G_ICMPMatt Arsenault2018-03-011-0/+67
| | | | | | Patch by Tom Stellard llvm-svn: 326472
* AMDGPU/GlobalISel: Make i32 mul legalMatt Arsenault2018-03-011-0/+18
| | | | llvm-svn: 326471
* AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEFMatt Arsenault2018-03-011-6/+27
| | | | | | Patch by Tom Stellard llvm-svn: 326470
* AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANTMatt Arsenault2018-03-011-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326468
* AMDGPU/GlobalISel: Make i32 xor legalMatt Arsenault2018-03-011-0/+18
| | | | llvm-svn: 326466
* AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legalMatt Arsenault2018-03-011-0/+35
| | | | | | Patch by Tom Stellard llvm-svn: 326465
* AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legalMatt Arsenault2018-03-011-0/+14
| | | | | | Patch by Tom Stellard llvm-svn: 326464
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