diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-01 20:40:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-01 20:40:55 +0000 |
| commit | 36b99e1937d07193e3463353dedf5f66616bafe5 (patch) | |
| tree | 55e3dda865e389f0019f074ed99496bea79e786d /llvm/test/CodeGen/AMDGPU | |
| parent | b34bd34fd27ec6c7d085421af035b6a3a93fe569 (diff) | |
| download | bcm5719-llvm-36b99e1937d07193e3463353dedf5f66616bafe5.tar.gz bcm5719-llvm-36b99e1937d07193e3463353dedf5f66616bafe5.zip | |
AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr
Patch by Tom Stellard
llvm-svn: 326479
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir new file mode 100644 index 00000000000..52aea1d351c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir @@ -0,0 +1,67 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- | + define void @exp_compr_v2f16_s() { + call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0) + ret void + } + define void @exp_compr_v2f16_v() { + call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0) + ret void + } + + declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) + declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) + +... + +--- +name: exp_compr_v2f16_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 + ; CHECK-LABEL: name: exp_compr_v2f16_s + ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false + ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[C2]](s1), [[C3]](s1) + %0:_(s32) = G_CONSTANT i32 0 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s32) = COPY $sgpr0 + %3:_(s32) = COPY $sgpr1 + %6:_(s1) = G_CONSTANT i1 0 + %7:_(s1) = G_CONSTANT i1 0 + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7 +... +--- +name: exp_compr_v2f16_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-LABEL: name: exp_compr_v2f16_v + ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false + ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false + ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY]](s32), [[COPY1]](s32), [[C2]](s1), [[C3]](s1) + %0:_(s32) = G_CONSTANT i32 0 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s32) = COPY $vgpr0 + %3:_(s32) = COPY $vgpr1 + %6:_(s1) = G_CONSTANT i1 0 + %7:_(s1) = G_CONSTANT i1 0 + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7 +... |
