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authorMatt Arsenault <Matthew.Arsenault@amd.com>2018-03-17 15:17:41 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2018-03-17 15:17:41 +0000
commit85803366d6dac06f32dee66c9fcd17b51cf3b3e3 (patch)
tree9c9a585c58a8fc31602530a5ef5474ab8617838c /llvm/test/CodeGen/AMDGPU
parent7e71129be40ab6ba56e6993da8f1646cd5061cf2 (diff)
downloadbcm5719-llvm-85803366d6dac06f32dee66c9fcd17b51cf3b3e3.tar.gz
bcm5719-llvm-85803366d6dac06f32dee66c9fcd17b51cf3b3e3.zip
AMDGPU/GlobalISel: Basic legality for load/store
llvm-svn: 327772
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
-rw-r--r--llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mir131
-rw-r--r--llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir122
2 files changed, 253 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mir
new file mode 100644
index 00000000000..a058530dbb9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mir
@@ -0,0 +1,131 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+---
+name: test_load_global_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[LOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 1)
+
+ $vgpr0 = COPY %1
+...
+
+---
+name: test_load_global_i64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[LOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 1)
+
+ $vgpr0 = COPY %1
+...
+
+---
+name: test_load_global_p1
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_p1
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(p1) = G_LOAD %0 :: (load 8, addrspace 1)
+
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_load_global_p4
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_p4
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(p4) = G_LOAD %0 :: (load 8, addrspace 1)
+
+ $vgpr0_vgpr1 = COPY %1
+...
+
+
+---
+name: test_load_global_p3
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_p3
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[LOAD]](p3)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(p3) = G_LOAD %0 :: (load 4, addrspace 1)
+
+ $vgpr0 = COPY %1
+...
+
+---
+name: test_load_global_v2s32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s32>) = G_LOAD %0 :: (load 8, addrspace 1)
+
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+
+name: test_load_global_v2s16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_v2s16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[LOAD]](<2 x s16>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = G_LOAD %0 :: (load 4, addrspace 1)
+ $vgpr0 = COPY %1
+...
+
+---
+name: test_load_global_v3i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_load_global_v3i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<3 x s32>) = G_LOAD %0 :: (load 12, align 4, addrspace 1)
+
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
new file mode 100644
index 00000000000..8d6696fe823
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
@@ -0,0 +1,122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+---
+name: test_store_global_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; CHECK-LABEL: name: test_store_global_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ G_STORE %1, %0 :: (store 4, addrspace 1)
+...
+
+---
+name: test_store_global_i64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_store_global_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store 8, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ G_STORE %1, %0 :: (store 8, addrspace 1)
+...
+
+---
+name: test_store_global_p1
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_store_global_p1
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr2_vgpr3
+ ; CHECK: G_STORE [[COPY1]](p1), [[COPY]](p1) :: (store 8, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(p1) = COPY $vgpr2_vgpr3
+ G_STORE %1, %0 :: (store 8, addrspace 1)
+...
+
+---
+name: test_store_global_p4
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_store_global_p4
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr2_vgpr3
+ ; CHECK: G_STORE [[COPY1]](p4), [[COPY]](p1) :: (store 8, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(p4) = COPY $vgpr2_vgpr3
+ G_STORE %1, %0 :: (store 8, addrspace 1)
+...
+
+---
+name: test_store_global_p3
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; CHECK-LABEL: name: test_store_global_p3
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
+ ; CHECK: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store 4, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(p3) = COPY $vgpr2
+ G_STORE %1, %0 :: (store 4, addrspace 1)
+...
+
+---
+name: test_store_global_v2s32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_store_global_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ ; CHECK: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store 8, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ G_STORE %1, %0 :: (store 8, addrspace 1)
+...
+
+---
+name: test_store_global_v2s16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; CHECK-LABEL: name: test_store_global_v2s16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+ ; CHECK: G_STORE [[COPY1]](<2 x s16>), [[COPY]](p1) :: (store 4, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s16>) = COPY $vgpr2
+ G_STORE %1, %0 :: (store 4, addrspace 1)
+...
+
+---
+name: test_store_global_v3s32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
+
+ ; CHECK-LABEL: name: test_store_global_v3s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
+ ; CHECK: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store 12, align 4, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
+ G_STORE %1, %0 :: (store 12, align 4, addrspace 1)
+...
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