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path: root/llvm/test/CodeGen/AMDGPU/sibling-call.ll
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* AMDGPU: Make s34 the FP registerMatt Arsenault2019-07-081-22/+27
* CodeGen: Set hasSideEffects = 0 on BUNDLEMatt Arsenault2019-07-031-5/+4
* AMDGPU: Always use s33 for global scratch wave offsetMatt Arsenault2019-06-201-5/+5
* AMDGPU: Don't fix emergency stack slot at offset 0Matt Arsenault2019-06-051-26/+29
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-051-30/+27
* AMDGPU: Activate all lanes when spilling CSR VGPR for SGPR spillsMatt Arsenault2019-05-241-3/+10
* [AMDGPU] Mark test functions with hidden visibilityScott Linder2019-02-011-2/+2
* AMDGPU: Generate VALU ThreeOp Integer instructionsNicolai Haehnle2018-12-061-2/+1
* [AMDGPU] Divergence driven instruction selection. Part 1.Alexander Timofeev2018-09-211-6/+6
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-3/+3
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-281-1/+1
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-9/+22
* AMDGPU: Enable IPRAMatt Arsenault2017-11-281-3/+3
* [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argumentYaxun Liu2017-11-221-26/+27
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky2017-11-201-6/+6
* AMDGPU: Make frame register caller preservedMatt Arsenault2017-09-141-1/+1
* AMDGPU: Don't spill SP reg like a normal CSRMatt Arsenault2017-09-131-0/+2
* AMDGPU: Fix not accounting for tail call resource usageMatt Arsenault2017-09-051-0/+31
* AMDGPU: Start adding tail call supportMatt Arsenault2017-08-111-0/+225
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