diff options
| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-11-20 18:24:21 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-11-20 18:24:21 +0000 |
| commit | a0342dc9eb9fe66e6287bdc3c0c0fa00deae652a (patch) | |
| tree | 63acfa36f2f66b449ebfef7f01e797ee6f19afee /llvm/test/CodeGen/AMDGPU/sibling-call.ll | |
| parent | 60cc1d3218fcecef98d307cee1a197d4649ccbfd (diff) | |
| download | bcm5719-llvm-a0342dc9eb9fe66e6287bdc3c0c0fa00deae652a.tar.gz bcm5719-llvm-a0342dc9eb9fe66e6287bdc3c0c0fa00deae652a.zip | |
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765
Reviewers: tamazov, SamWot, arsenm, vpykhtin
Differential Revision: https://reviews.llvm.org/D40088
llvm-svn: 318675
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/sibling-call.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/sibling-call.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll index 833de07095b..1fca5499883 100644 --- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll +++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll @@ -4,7 +4,7 @@ ; GCN-LABEL: {{^}}i32_fastcc_i32_i32: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v0 ; GCN-NEXT: s_setpc_b64 define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 { %add0 = add i32 %arg0, %arg1 @@ -13,7 +13,7 @@ define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 { ; GCN-LABEL: {{^}}i32_fastcc_i32_i32_stack_object: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN: v_add_i32_e32 v0, vcc, v1, v +; GCN: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v ; GCN: s_mov_b32 s5, s32 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:24 ; GCN: s_waitcnt vmcnt(0) @@ -83,7 +83,7 @@ entry: ; GCN-NEXT: s_mov_b32 s5, s32 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s5 offset:4 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] define fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32* byval align 4 %arg1) #1 { %arg1.load = load i32, i32* %arg1, align 4 @@ -122,9 +122,9 @@ entry: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s5 offset:4 ; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s5 offset:8 -; GCN-DAG: v_add_i32_e32 v0, vcc, v1, v0 -; GCN: v_add_i32_e32 v0, vcc, [[LOAD_0]], v0 -; GCN: v_add_i32_e32 v0, vcc, [[LOAD_1]], v0 +; GCN-DAG: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v0 +; GCN: v_add_{{[_coiu]*}}32_e32 v0, vcc, [[LOAD_0]], v0 +; GCN: v_add_{{[_coiu]*}}32_e32 v0, vcc, [[LOAD_1]], v0 ; GCN-NEXT: s_setpc_b64 define fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %arg0, i32 %arg1, [32 x i32] %large) #1 { %val_firststack = extractvalue [32 x i32] %large, 30 |
