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* AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)Jan Vesely2020-02-101-14/+24
* AMDGPU: Fix handling of infinite loops in fragment shadersConnor Abbott2020-02-041-0/+68
* R600: Fix failing testcaseMatt Arsenault2020-02-031-3/+3
* AMDGPU/R600: Emit rodata in text segmentJan Vesely2020-02-031-0/+6
* Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle2020-02-0334-217/+374
* [AMDGPU] Invert the handling of skip insertion.cdevadas2020-01-1534-374/+217
* [amdgpu] Fix typos in a test case.Michael Liao2020-01-141-1/+0
* [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.Michael Liao2020-01-1412-355/+329
* [DAGCombine] Replace `getIntPtrConstant()` with `getVectorIdxTy()`.Michael Liao2020-01-141-0/+40
* [MachineScheduler] Reduce reordering due to mem op clusteringJay Foad2020-01-1415-94/+95
* [AMDGPU] Model distance to instruction in bundleStanislav Mekhanoshin2020-01-141-0/+44
* [AMDGPU] Fix getInstrLatency() always returning 1Stanislav Mekhanoshin2020-01-142-4/+5
* AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}Matt Arsenault2020-01-133-0/+11
* AMDGPU/GlobalISel: Add some baseline tests for vector extractMatt Arsenault2020-01-131-0/+468
* AMDGPU/GlobalISel: Fix branch targets when emitting SI_IFMatt Arsenault2020-01-131-0/+61
* GlobalISel: Fix assertion on wide G_ZEXT sourcesMatt Arsenault2020-01-131-0/+25
* [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/...Simon Pilgrim2020-01-133-40/+34
* AMDGPU: Split test functionMatt Arsenault2020-01-121-4/+16
* AMDGPU/GlobalISel: Don't use XEXEC class for SGPRsMatt Arsenault2020-01-1238-196/+193
* AMDGPU/GlobalISel: Copy type when inserting readfirstlaneMatt Arsenault2020-01-128-29/+29
* [AMDGPU] Regenerate shl shift testsSimon Pilgrim2020-01-121-244/+1473
* [AMDGPU] Remove unnecessary v_mov from a register to itself in WQM lowering.Michael Bedy2020-01-102-0/+62
* AMDGPU/GlobalISel: Clamp G_ZEXT source sizesMatt Arsenault2020-01-107-238/+967
* AMDGPU/GlobalISel: Select G_EXTRACT_VECTOR_ELTMatt Arsenault2020-01-092-0/+2099
* AMDGPU/GlobalISel: Fix G_EXTRACT_VECTOR_ELT mapping for s-v caseMatt Arsenault2020-01-091-10/+16
* [AMDGPU] Fix bundle schedulingStanislav Mekhanoshin2020-01-0916-31/+31
* TableGen/GlobalISel: Add way for SDNodeXForm to work on timmMatt Arsenault2020-01-091-0/+46
* GlobalISel: Handle llvm.read_registerMatt Arsenault2020-01-091-0/+2
* AMDGPU/GlobalISel: Fix argument lowering for vectors of pointersMatt Arsenault2020-01-091-14/+116
* AMDGPU/GlobalISel: Widen 16-bit shift amount sourcesMatt Arsenault2020-01-093-80/+94
* AMDGPU/GlobalISel: Fix import of integer med3Matt Arsenault2020-01-094-0/+616
* AMDGPU/GlobalISel: Fix import of zext of s16 op patternsMatt Arsenault2020-01-094-12/+138
* AMDGPU/GlobalISel: Fix add of neg inline constant patternMatt Arsenault2020-01-091-0/+113
* Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders2020-01-0811-194/+194
* Revert "[MIR] Target specific MIR formating and parsing"Nico Weber2020-01-0811-194/+194
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-0811-194/+194
* Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders2020-01-0811-194/+194
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-0811-194/+194
* AMDGPU/GlobalISel: Fix scalar G_SELECT for arbitrary pointersMatt Arsenault2020-01-072-1/+97
* AMDGPU/GlobalISel: Add some missing G_SELECT testcasesMatt Arsenault2020-01-071-0/+142
* AMDGPU/GlobalISel: Fix missing test for s16 icmpMatt Arsenault2020-01-071-0/+236
* AMDGPU: Apply i16 add->sub pattern with zext to i32Matt Arsenault2020-01-072-13/+13
* AMDGPU: Add baseline test for missing patternMatt Arsenault2020-01-071-0/+583
* AMDGPU: Fix not using v_cvt_f16_[iu]16Matt Arsenault2020-01-074-21/+24
* AMDGPU/GlobalISel: Fix readfirstlane pattern importMatt Arsenault2020-01-071-0/+63
* AMDGPU/GlobalISel: Fix import of s_abs_i32 patternMatt Arsenault2020-01-071-0/+105
* AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.voteMatt Arsenault2020-01-072-6/+18
* llc: Change behavior of -mcpu with existing attributeMatt Arsenault2020-01-071-8/+3
* AMDGPU: Add run line to int_to_fp testsMatt Arsenault2020-01-062-57/+109
* AMDGPU/GlobalISel: Legalize G_READCYCLECOUNTERMatt Arsenault2020-01-061-0/+3
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