| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir... | Guillaume Chatelet | 2019-09-11 | 1 | -1/+1 |
| * | [AMDGPU] gfx1010 VMEM and SMEM implementation | Stanislav Mekhanoshin | 2019-04-30 | 1 | -3/+3 |
| * | Followup on Proposal to move MIR physical register namespace to '$' sigil. | Puyan Lotfi | 2018-01-31 | 1 | -8/+8 |
| * | AMDGPU: Start adding offset fields to flat instructions | Matt Arsenault | 2017-06-12 | 1 | -3/+3 |
| * | Vivek Pandya | 2017-06-06 | 1 | -7/+7 | |
| * | AMDGPU: Remove tfe bit from flat instruction definitions | Matt Arsenault | 2017-05-11 | 1 | -3/+3 |
| * | [AMDGPU] Do not allow register coalescer to create big superregs | Stanislav Mekhanoshin | 2017-01-18 | 1 | -0/+71 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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