bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes ↵	Guillaume Chatelet	2019-09-11	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
*	[AMDGPU] gfx1010 VMEM and SMEM implementation	Stanislav Mekhanoshin	2019-04-30	1	-3/+3
\| \| \| \| \| \|	Differential Revision: https://reviews.llvm.org/D61330 llvm-svn: 359621
*	Followup on Proposal to move MIR physical register namespace to '$' sigil.	Puyan Lotfi	2018-01-31	1	-8/+8
\| \| \| \| \| \| \| \| \| \| \| \|	Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
*	AMDGPU: Start adding offset fields to flat instructions	Matt Arsenault	2017-06-12	1	-3/+3
\| \| \| \|	llvm-svn: 305194
*		Vivek Pandya	2017-06-06	1	-7/+7
\| \| \| \| \| \| \| \| \| \| \| \|	[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. If -simplify-mir option is passed then MIRPrinter will not print such fields. This change also required some lit test cases in CodeGen directory to be changed. Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D32304 llvm-svn: 304779
*	AMDGPU: Remove tfe bit from flat instruction definitions	Matt Arsenault	2017-05-11	1	-3/+3
\| \| \| \| \| \| \| \| \| \|	We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. llvm-svn: 302814
*	[AMDGPU] Do not allow register coalescer to create big superregs	Stanislav Mekhanoshin	2017-01-18	1	-0/+71
	Limit register coalescer by not allowing it to artificially increase size of registers beyond dword. Such super-registers are in fact register sequences and not distinct HW registers. With more super-regs we would need to allocate adjacent registers and constraint regalloc more than needed. Moreover, our super registers are overlapping. For instance we have VGPR0_VGPR1_VGPR2, VGPR1_VGPR2_VGPR3, VGPR2_VGPR3_VGPR4 etc, which complicates registers allocation even more, resulting in excessive spilling. Differential Revision: https://reviews.llvm.org/D28782 llvm-svn: 292413