Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | AMDGPU/GlobalISel: Replace handling of boolean values | Matt Arsenault | 2020-01-06 | 1 | -53/+32 |
* | AMDGPU/GlobalISel: Fix missing scc imp-def on scalar and/or/xor | Matt Arsenault | 2019-12-21 | 1 | -20/+20 |
* | AMDGPU: Relax 32-bit SGPR register class | Matt Arsenault | 2019-10-18 | 1 | -33/+33 |
* | AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor | Matt Arsenault | 2019-09-30 | 1 | -15/+15 |
* | AMDGPU/GlobalISel: Select 16-bit VALU bit ops | Matt Arsenault | 2019-09-13 | 1 | -6/+5 |
* | AMDGPU/GlobalISel: Fix constraining scalar and/or/xor | Matt Arsenault | 2019-08-28 | 1 | -56/+81 |
* | AMDGPU/GlobalISel: Fix test failures in release build | Matt Arsenault | 2019-07-16 | 1 | -12/+9 |
* | AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR | Matt Arsenault | 2019-07-15 | 1 | -0/+593 |