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path: root/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
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* AArch64: avoid creating cycle in DAG for post-increment NEON ops.Tim Northover2019-08-271-0/+19
* [AArch64] Prefer "mov" over "orr" to materialize constants.Eli Friedman2019-03-251-10/+10
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-1/+1
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-1/+1
* [AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16Adam Nemet2017-04-131-0/+81
* [AArch64] Avoid partial register deps on insertelt of load into lane 0.Ahmed Bougacha2017-04-041-5/+5
* Revert r294437 as it broke an asan buildbot.Amara Emerson2017-02-081-1/+1
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-081-1/+1
* [AArch64] Handle vector types in replaceZeroVectorStore.Geoff Berry2016-11-161-3/+2
* [AArch64] Enable PostRAScheduler for AArch64 generic build.Chad Rosier2015-12-211-1/+1
* AArch64: Fix loads to lower NEON vector lanes using GPR registersMatthias Braun2015-08-311-0/+24
* [AArch64] Don't force MVT::Untyped when selecting LD1LANEpost.Ahmed Bougacha2015-04-171-0/+22
* Fix another typo in r235224 testcase. NFC.Ahmed Bougacha2015-04-171-9/+9
* Fix typo in r235224 testcase. NFC.Ahmed Bougacha2015-04-171-1/+1
* [AArch64] Avoid vector->load dependency cycles when creating LD1*post.Ahmed Bougacha2015-04-171-1/+22
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-62/+62
* [opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie2015-02-271-610/+610
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+6174
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