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* [AArch64] Change AArch64 Windows EH UnwindHelp object to be a fixed objectDaniel Frampton2020-06-255-24/+92
* [AArch64] Fix mismatch in prologue and epilogue for funclets on WindowsDaniel Frampton2020-06-251-0/+62
* [AARch64] Add Marvell ThunderX3T110 supportWei Zhao2020-06-175-0/+5
* [AArch64] Fix BTI instruction emission.Daniel Kiss2020-06-161-2/+10
* [AArch64] Fix BTI landing pad generation.Daniel Kiss2020-06-161-0/+31
* No longer generate calls to *_finiteserge-sans-paille2020-02-281-12/+12
* [Codegen] Revert rL354676/rL354677 and followups - introduced PR43446 miscompileRoman Lebedev2020-02-261-4/+27
* [AArch64][FPenv] Update chain of int to fp conversionDiogo Sampaio2020-02-181-0/+67
* [FPEnv][AArch64] Add lowering of f128 STRICT_FSETCCJohn Brawn2020-02-181-1/+191
* [FPEnv][AArch64] Add lowering and instruction selection for strict conversionsJohn Brawn2020-02-182-39/+410
* [FPEnv][AArch64] Add lowering and instruction selection for STRICT_FP_ROUNDJohn Brawn2020-02-181-3/+18
* Add lowering of STRICT_FSETCC and STRICT_FSETCCSJohn Brawn2020-02-181-0/+974
* Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field"Jeremy Morse2020-02-122-5/+5
* [AArch64] Add option to enable/disable load-store renaming.Florian Hahn2020-02-108-15/+21
* [X86] -fpatchable-function-entry=N,0: place patch label after ENDBR{32,64}Fangrui Song2020-02-051-2/+4
* [ARM][VecReduce] Force expand vector_reduce_fminDavid Green2020-02-051-1/+1
* [AArch64][ARM] Always expand ordered vector reductions (PR44600)Nikita Popov2020-02-053-0/+330
* [AArch64] -fpatchable-function-entry=N,0: place patch label after BTIFangrui Song2020-02-031-2/+43
* Drop arm triple from test/CodeGen/AArch64/global-merge-hidden-minsize.llHans Wennborg2020-01-301-1/+0
* [GlobalMerge] Preserve symbol visibility when merging globalsMichael Spang2020-01-291-0/+26
* [PatchableFunction] Allow empty entry MachineBasicBlockFangrui Song2020-01-241-0/+64
* Add function attribute "patchable-function-prefix" to support -fpatchable-fun...Fangrui Song2020-01-242-13/+73
* [AsmPrinter] Don't emit __patchable_function_entries entry if "patchable-func...Fangrui Song2020-01-242-16/+24
* [CodeGen] Move fentry-insert, xray-instrumentation and patchable-function bef...Fangrui Song2020-01-243-6/+30
* [AArch64] Don't rename registers with pseudo defs in Ld/St opt.Florian Hahn2020-01-221-0/+33
* Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: S...Simon Pilgrim2020-01-152-42/+0
* [AArch64][SVE] Add ptest intrinsicsCullen Rhodes2020-01-152-0/+62
* [AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.Amara Emerson2020-01-142-0/+42
* [SVE] Add patterns for MUL immediate instruction.Danilo Carvalho Grael2020-01-143-0/+106
* [MachineScheduler] Reduce reordering due to mem op clusteringJay Foad2020-01-146-20/+20
* [AArch64] Fix save register pairing for Windows AAPCSSanne Wouda2020-01-141-0/+35
* [GlobalISel] Change representation of shuffle masks in MachineOperand.Eli Friedman2020-01-131-2/+2
* [AArch64][SVE] Add patterns for some arith SVE instructions.Danilo Carvalho Grael2020-01-131-0/+365
* [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or belowPablo Barrio2020-01-1311-99/+185
* [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/...Simon Pilgrim2020-01-132-9/+4
* This option allows selecting the TLS size in the local exec TLS model,KAWASHIMA Takahiro2020-01-132-45/+106
* __patchable_function_entries: don't use linkage field 'unique' with -no-integ...Fangrui Song2020-01-121-0/+1
* [AArch64] Don't generate libcalls for wide shifts on DarwinJessica Paquette2020-01-101-0/+5
* [AArch64] Add function attribute "patchable-function-entry" to add NOPs at fu...Fangrui Song2020-01-101-0/+55
* Add support for __declspec(guard(nocf))Andrew Paverd2020-01-101-5/+5
* Relax opcode checks in test for G_READCYCLECOUNTER to check for only a number...Douglas Yung2020-01-091-1/+1
* [AArch64][GlobalISel] Implement selection of <2 x float> vector splat.Amara Emerson2020-01-093-6/+71
* [GlobalISel][AArch64] Import + select LDR*roW and STR*roW patternsJessica Paquette2020-01-092-0/+483
* Revert "Merge memtag instructions with adjacent stack slots."Evgenii Stepanov2020-01-084-308/+13
* Merge memtag instructions with adjacent stack slots.Evgenii Stepanov2020-01-084-13/+308
* AArch64: add missing Apple CPU names and use them by default.Tim Northover2020-01-081-0/+1
* [AArch64][GlobalISel] Fold a chain of two G_PTR_ADDs of constant offsets.Amara Emerson2020-01-071-0/+72
* [MachineOutliner][AArch64] Save + restore LR in noreturn functionsJessica Paquette2020-01-072-56/+103
* Lower TAGPstack with negative offset to SUBG.Evgenii Stepanov2020-01-061-0/+37
* GlobalISel: Define G_READCYCLECOUNTERMatt Arsenault2020-01-042-0/+15
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