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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-04-04 22:55:53 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-04-04 22:55:53 +0000 |
| commit | d3c03a5ddd9523386ef766a397483d09a60f7156 (patch) | |
| tree | aae82cca474dc693b9f0f1257dbe6c0cab892b6c /llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll | |
| parent | e73e00c9b29b3d9b28b728849b06ed6b0b9bea88 (diff) | |
| download | bcm5719-llvm-d3c03a5ddd9523386ef766a397483d09a60f7156.tar.gz bcm5719-llvm-d3c03a5ddd9523386ef766a397483d09a60f7156.zip | |
[AArch64] Avoid partial register deps on insertelt of load into lane 0.
This improves upon r246462: that prevented FMOVs from being emitted
for the cross-class INSERT_SUBREGs by disabling the formation of
INSERT_SUBREGs of LOAD. But the ld1.s that we started selecting
caused us to introduce partial dependencies on the vector register.
Avoid that by using SCALAR_TO_VECTOR: it's a first-class citizen that
is folded away by many patterns, including the scalar LDRS that we
want in this case.
Credit goes to Adam for finding the issue!
llvm-svn: 299482
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll index 071b2d0dbca..d344084ef62 100644 --- a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll +++ b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll @@ -6216,11 +6216,11 @@ define <4 x i16> @test_v4i16_post_reg_ld1lane_forced_narrow(i16* %bar, i16** %pt declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) ; CHECK-LABEL: test_ld1lane_build: -; CHECK-DAG: ld1.s { [[REG0:v[0-9]+]] }[0], [x0] -; CHECK-DAG: ld1.s { [[REG0:v[0-9]+]] }[1], [x1] -; CHECK-DAG: ld1.s { [[REG1:v[0-9]+]] }[0], [x2] -; CHECK-DAG: ld1.s { [[REG1:v[0-9]+]] }[1], [x3] -; CHECK: sub.2s v[[REGNUM2:[0-9]+]], [[REG0]], [[REG1]] +; CHECK-DAG: ldr s[[REGNUM0:[0-9]+]], [x0] +; CHECK-DAG: ld1.s { v[[REGNUM0:[0-9]+]] }[1], [x1] +; CHECK-DAG: ldr s[[REGNUM1:[0-9]+]], [x2] +; CHECK-DAG: ld1.s { v[[REGNUM1:[0-9]+]] }[1], [x3] +; CHECK: sub.2s v[[REGNUM2:[0-9]+]], v[[REGNUM0]], v[[REGNUM1]] ; CHECK-NEXT: str d[[REGNUM2]], [x4] ; CHECK-NEXT: ret define void @test_ld1lane_build(i32* %ptr0, i32* %ptr1, i32* %ptr2, i32* %ptr3, <2 x i32>* %out) { |
