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* NFC: Use range-based for loops and more consistent naming.Daniel Jasper2015-02-181-19/+15
| | | | | | | | | No functional changes intended. (I plan on doing some modifications to this function and would like to have as few unrelated changes as possible in the patch) llvm-svn: 229649
* Remove experimental options to control machine block placement.Daniel Jasper2015-02-181-35/+20
| | | | | | | This reverts r226034. Benchmarking with those flags has not revealed anything interesting. llvm-svn: 229648
* Address post commit review on r229600.Sanjoy Das2015-02-181-2/+2
| | | | llvm-svn: 229646
* AVX-512: Added support for FP instructions with embedded rounding mode.Elena Demikhovsky2015-02-185-12/+73
| | | | | | By Asaf Badouh <asaf.badouh@intel.com> llvm-svn: 229645
* [x86] Rewrite the byte shift detection to not use boolean variables toChandler Carruth2015-02-181-22/+21
| | | | | | | | | | | | | | | | | | | | | | | track state. I didn't like this in the code review because the pattern tends to be error prone, but I didn't see a clear way to rewrite it. Turns out that there were bugs here, I found them when fuzz testing our shuffle lowering for correctness on x86. The core of the problem is that we need to consistently test all our preconditions for the same directionality of shift and the same input vector. Instead, formulate this as two predicates (one doesn't depend on the input in any way), pass things like the directionality and input vector as inputs, and loop over the alternatives. This fixes a pattern of very rare miscompiles coming out of this code. Turned up roughly 4 out of every 1 million v8 shuffles in my fuzz testing. The new code is over half a million test runs with no failures yet. I've also fuzzed every other function in the lowering code with over 3.5 million test cases and not discovered any other miscompiles. llvm-svn: 229642
* [X86] Remove AVX512 pslldq/psrldq shift intrinsics. They aren't implemented ↵Craig Topper2015-02-181-6/+0
| | | | | | yet and when they are they should be done with shuffles like SSE2 and AVX2. llvm-svn: 229641
* [X86] Remove AVX2 and SSE2 pslldq and psrldq intrinsics. We can represent ↵Craig Topper2015-02-183-98/+110
| | | | | | them in IR with vector shuffles now. All their uses have been removed from clang in favor of shuffles. llvm-svn: 229640
* Analysis: fix buildbotsSaleem Abdulrasool2015-02-181-1/+1
| | | | | | | This should fix the compilation failure on the MSVC buildbots which find a std::make_unique and llvm::make_unique via ADL, resulting in ambiguity. llvm-svn: 229638
* [LoopAccesses] Change LAA:getInfo to return a constant referenceAdam Nemet2015-02-182-6/+7
| | | | | | | | As expected, this required a few more const-correctness fixes. Based on Hal's feedback on D7684. llvm-svn: 229634
* [LoopAccesses] Add -analyze supportAdam Nemet2015-02-181-0/+51
| | | | | | | | | | | | | | | | The LoopInfo in combination with depth_first is used to enumerate the loops. Right now -analyze is not yet complete. It only prints the result of the analysis, the report and the run-time checks. Printing the unsafe depedences will require a bit more reshuffling which I'd like to do in a follow-on to this patchset. Unsafe dependences are currently checked via -debug-only=loop-accesses in the new test. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229633
* [LoopAccesses] Split out LoopAccessReport from VectorizerReportAdam Nemet2015-02-182-25/+44
| | | | | | | | | | | | The only difference between these two is that VectorizerReport adds a vectorizer-specific prefix to its messages. When LAA is used in the vectorizer context the prefix is added when we promote the LoopAccessReport into a VectorizerReport via one of the constructors. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229632
* [LoopAccesses] Add missing const to APIs in VectorizationReportAdam Nemet2015-02-182-4/+4
| | | | | | | | | | When I split out LoopAccessReport from this, I need to create some temps so constness becomes necessary. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229631
* [LoopAccesses] Add canAnalyzeLoopAdam Nemet2015-02-181-1/+51
| | | | | | | | | | | This allows the analysis to be attempted with any loop. This feature will be used with -analysis. (LV only requests the analysis on loops that have already satisfied these tests.) This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229630
* [LoopAccesses] Factor out RuntimePointerCheck::needsCheckingAdam Nemet2015-02-181-9/+18
| | | | | | | | | Will be used by the new RuntimePointerCheck::print. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229629
* [LoopAccesses] Change debug messages from LV to LAAAdam Nemet2015-02-182-40/+41
| | | | | | | | | Also add pass name as an argument to VectorizationReport::emitAnalysis. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229628
* [LoopAccesses] Create the analysis passAdam Nemet2015-02-183-17/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a function pass that runs the analysis on demand. The analysis can be initiated by querying the loop access info via LAA::getInfo. It either returns the cached info or runs the analysis. Symbolic stride information continues to reside outside of this analysis pass. We may move it inside later but it's not a priority for me right now. The idea is that Loop Distribution won't support run-time stride checking at least initially. This means that when querying the analysis, symbolic stride information can be provided optionally. Whether stride information is used can invalidate the cache entry and rerun the analysis. Note that if the loop does not have any symbolic stride, the entry should be preserved across Loop Distribution and LV. Since currently the only user of the pass is LV, I just check that the symbolic stride information didn't change when using a cached result. On the LV side, LoopVectorizationLegality requests the info object corresponding to the loop from the analysis pass. A large chunk of the diff is due to LAI becoming a pointer from a reference. A test will be added as part of the -analyze patch. Also tested that with AVX, we generate identical assembly output for the testsuite (including the external testsuite) before and after. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229626
* [LoopAccesses] Make blockNeedsPredication staticAdam Nemet2015-02-182-5/+8
| | | | | | | | | | | | | | | | blockNeedsPredication is in LoopAccess in order to share it with the vectorizer. It's a utility needed by LoopAccess not strictly provided by it but it's a good place to share it. This makes the function static so that it no longer required to create an LoopAccessInfo instance in order to access it from LV. This was actually causing problems because it would have required creating LAI much earlier that LV::canVectorizeMemory(). This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229625
* [LoopAccesses] Cache the result of canVectorizeMemoryAdam Nemet2015-02-182-15/+22
| | | | | | | | | | | | LAA will be an on-demand analysis pass, so we need to cache the result of the analysis. canVectorizeMemory is renamed to analyzeLoop which computes the result. canVectorizeMemory becomes the query function for the cached result. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229624
* [LoopAccesses] Stash the report from the analysis rather than emitting itAdam Nemet2015-02-182-3/+8
| | | | | | | | | | | The transformation passes will query this and then emit them as part of their own report. The currently only user LV is modified to do just that. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229623
* [LoopAccesses] Make VectorizerParams globalAdam Nemet2015-02-182-31/+33
| | | | | | | | | | | | | | As LAA is becoming a pass, we can no longer pass the params to its constructor. This changes the command line flags to have external storage. These can now be accessed both from LV and LAA. VectorizerParams is moved out of LoopAccessInfo in order to shorten the code to access it. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229622
* [LoopAccesses] Rename LoopAccessAnalysis to LoopAccessInfoAdam Nemet2015-02-182-30/+29
| | | | | | | | | LoopAccessAnalysis will be used as the name of the pass. This is part of the patchset that converts LoopAccessAnalysis into an actual analysis pass. llvm-svn: 229621
* [InstCombine] Do not insert a GEP instruction before a landingpad instruction.Akira Hatanaka2015-02-181-4/+4
| | | | | | | | | | | InstCombiner::visitGetElementPtrInst was using getFirstNonPHI to compute the insertion point, which caused the verifier to complain when a GEP was inserted before a landingpad instruction. This commit fixes it to use getFirstInsertionPt instead. rdar://problem/19394964 llvm-svn: 229619
* [BDCE] Don't forget uses of root instructions seen before the instruction itselfHal Finkel2015-02-181-3/+6
| | | | | | | | | | | | | | | | | When visiting the initial list of "root" instructions (those which must always be alive), for those that are integer-valued (such as invokes returning an integer), we mark their bits as (initially) all dead (we might, obviously, find uses of those bits later, but all bits are assumed dead until proven otherwise). Don't do so, however, if we're already seen a use of those bits by another root instruction (such as a store). Fixes a miscompile of the sanitizer unit tests on x86_64. Also, add a debug line for visiting the root instructions, and remove a debug line which tried to print instructions being removed (printing dead instructions is dangerous, and can sometimes crash). llvm-svn: 229618
* R600/SI: Rename dst encoding field to be consistent with docsMatt Arsenault2015-02-182-4/+4
| | | | | | The docs call this vdst instead of just dst. llvm-svn: 229614
* R600/SI: Consistently capitalize encoding field namesMatt Arsenault2015-02-183-142/+119
| | | | | | | | | | Some formats capitalized these, but most didn't. Change them all to be consistently lowercase. Now, non-encoding fields and convenience bits are capitalized. Also remove weird looking empty line in some of the formats. llvm-svn: 229613
* R600/SI: Set noNamedPositionallyEncodedOperandsMatt Arsenault2015-02-181-0/+1
| | | | llvm-svn: 229612
* R600/SI: Fix src1_modifiers for class instructionsMatt Arsenault2015-02-181-2/+26
| | | | | | | | src1 doesn't have modifiers, but the operand was missing resulting in an encoding build error when all fields are required.' llvm-svn: 229611
* R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64Matt Arsenault2015-02-182-3/+5
| | | | | | | Rename the multiclass since it now applies to the output modifiers as well. llvm-svn: 229610
* R600: Fix operand encoding errorMatt Arsenault2015-02-181-0/+1
| | | | llvm-svn: 229609
* R600/SI: Fix encoding error from glc bit on VI SMRD instructionsMatt Arsenault2015-02-181-1/+5
| | | | llvm-svn: 229608
* R600/SI: Fix operand encoding for flat instructionsMatt Arsenault2015-02-181-2/+4
| | | | llvm-svn: 229607
* R600/SI: Fix error from vdst on no return atomicsMatt Arsenault2015-02-181-3/+5
| | | | | | | Set the ignored field to 0 so we can enable noNamedPositionallyEncodedOperands. llvm-svn: 229606
* R600/SI: Add missing offset operand to buffer bothenMatt Arsenault2015-02-182-4/+4
| | | | llvm-svn: 229605
* R600/SI: Add missing soffset operand to global atomicsMatt Arsenault2015-02-181-2/+2
| | | | llvm-svn: 229604
* R600/SI: Fix brace identationMatt Arsenault2015-02-181-1/+1
| | | | llvm-svn: 229603
* Re-apply "InstrProf: Add unit tests for the profile reader and writer"Justin Bogner2015-02-182-14/+46
| | | | | | | | | | | | | | Have the InstrProfWriter return a MemoryBuffer instead of a std::string. This fixes the alignment issues the reader would hit, and it's a more appropriate type for this anyway. I've also removed an ugly helper function that's not needed since we're allowing initializer lists now, and updated some error code checks based on MSVC's issues with r229473. This reverts r229483, reapplying r229478. llvm-svn: 229602
* LiveRangeCalc: Rename some parameters from kill to use, NFC.Matthias Braun2015-02-183-36/+35
| | | | | | Those parameters did not necessarily describe kill points but just uses. llvm-svn: 229601
* Generalize getExtendAddRecStart to work with both sign and zeroSanjoy Das2015-02-181-143/+218
| | | | | | | | | | | extensions. This change also removes `DEBUG(dbgs() << "SCEV: untested prestart overflow check\n");` because that case has a unit test now. Differential Revision: http://reviews.llvm.org/D7645 llvm-svn: 229600
* Make the Mips AsmPrinter independent of global subtargetEric Christopher2015-02-182-11/+23
| | | | | | | | | | | | | | initialization. Initialize the subtarget once per function and migrate EmitStartOfAsmFile to either use calls on the TargetMachine or get information from the subtarget we'd use for assembling. The top-level-ness of the MIPS attribute output for assembly is, by nature, contrary to how we'd want to do this for an LTO situation where we have multiple cpu architectures so this solution is good enough for now. llvm-svn: 229596
* Unify selectMipsCPU implementations.Eric Christopher2015-02-183-20/+11
| | | | llvm-svn: 229595
* Bugfix: SCEV incorrectly marks certain expressions as nswSanjoy Das2015-02-181-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I could not come up with a test case for this one; but I don't think `getPreStartForSignExtend` can assume `AR` is `nsw` -- there is one place in scalar evolution that calls `getSignExtendAddRecStart(AR, ...)` without proving that `AR` is `nsw` (line 1564) OperandExtendedAdd = getAddExpr(WideStart, getMulExpr(WideMaxBECount, getZeroExtendExpr(Step, WideTy))); if (SAdd == OperandExtendedAdd) { // If AR wraps around then // // abs(Step) * MaxBECount > unsigned-max(AR->getType()) // => SAdd != OperandExtendedAdd // // Thus (AR is not NW => SAdd != OperandExtendedAdd) <=> // (SAdd == OperandExtendedAdd => AR is NW) const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNW); // Return the expression with the addrec on the outside. return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this), getZeroExtendExpr(Step, Ty), L, AR->getNoWrapFlags()); } Differential Revision: http://reviews.llvm.org/D7640 llvm-svn: 229594
* Twines should be passed by const ref.Rafael Espindola2015-02-171-2/+2
| | | | llvm-svn: 229590
* [X86][FastIsel] Teach how to select scalar integer to float/double conversions.Andrea Di Biagio2015-02-171-0/+48
| | | | | | | | | | | | This patch teaches fast-isel how to select a (V)CVTSI2SSrr for an integer to float conversion, and how to select a (V)CVTSI2SDrr for an integer to double conversion. Added test 'fast-isel-int-float-conversion.ll'. Differential Revision: http://reviews.llvm.org/D7698 llvm-svn: 229589
* Add r228939 back with a fix.Rafael Espindola2015-02-173-11/+29
| | | | | | | | | | | | | The problem in the original patch was not switching back to .text after printing an eh table. Original message: On ELF, put PIC jump tables in a non executable section. Fixes PR22558. llvm-svn: 229586
* rename variables again because these tables also deal with stores; NFCSanjay Patel2015-02-171-31/+31
| | | | | | Suggestion by Simon Pilgrim llvm-svn: 229574
* IR: fieldIsMDNode() should be false for MDStringDuncan P. N. Exon Smith2015-02-171-8/+1
| | | | | | | Simplify the code. It has been a while since the schema has been so "flexible". llvm-svn: 229573
* AsmPrinter: Take range in DwarfExpression::AddExpression(), NFCDuncan P. N. Exon Smith2015-02-174-6/+11
| | | | | | | | | | Previously `DwarfExpression::AddExpression()` relied on default-constructing the end iterators for `DIExpression` -- once the operands are represented explicitly via `MDExpression` (instead of via the strange `StringRef` navigator in `DIHeaderIterator`) this won't work. Explicitly take an iterator for the end of the range. llvm-svn: 229572
* [X86][SSE] Generalised unpckl/unpckh shuffle matchingSimon Pilgrim2015-02-171-0/+24
| | | | | | | | Added commuted unpckl/unpckh shuffle matching patterns as many cases containing undefined lanes fail to commute by themselves. Differential Revision: http://reviews.llvm.org/D7564 llvm-svn: 229571
* Add comment to explain a non-obvious setting; NFC.Sanjay Patel2015-02-171-0/+6
| | | | | | | This is paraphrased from Simon Pilgrim's comment in: http://reviews.llvm.org/D7492 llvm-svn: 229566
* remove function names from comments; NFCSanjay Patel2015-02-171-38/+31
| | | | llvm-svn: 229558
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