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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-02-18 02:10:40 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-02-18 02:10:40 +0000 |
| commit | 1991f5e40bb6514038191b35bdcfce8be2432d12 (patch) | |
| tree | 9ffa739291e5f7b576120ec2d9bb9c0e53aabf51 /llvm/lib | |
| parent | e6c5241814c99f4e5ce7875de540536ab186d26a (diff) | |
| download | bcm5719-llvm-1991f5e40bb6514038191b35bdcfce8be2432d12.tar.gz bcm5719-llvm-1991f5e40bb6514038191b35bdcfce8be2432d12.zip | |
R600/SI: Fix encoding error from glc bit on VI SMRD instructions
llvm-svn: 229608
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.td | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 520379225d9..3443d4ba9ee 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -576,7 +576,11 @@ multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins, def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>; - def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>; + // glc is only applicable to scalar stores, which are not yet + // implemented. + let glc = 0 in { + def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>; + } } multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass, |
