summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Lowering x86 adds/addus/subs/subus intrinsics (llvm part)Alexander Ivchenko2018-04-193-42/+193
| | | | | | | | | | | | | This is the patch that lowers x86 intrinsics to native IR in order to enable optimizations. The patch also includes folding of previously missing saturation patterns so that IR emits the same machine instructions as the intrinsics. Patch by tkrupa Differential Revision: https://reviews.llvm.org/D44785 llvm-svn: 330322
* [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides.Simon Pilgrim2018-04-194-25/+1
| | | | | | These are all already handled identically by WriteFMA. llvm-svn: 330319
* [X86][BtVer2] Remove 128-bit F16C InstRW overrides.Simon Pilgrim2018-04-191-10/+0
| | | | | | These are already handled identically by WriteCvtF2F. llvm-svn: 330318
* [BasicBlock] Add instructionsWithoutDebug methods to skip debug insts.Florian Hahn2018-04-191-0/+18
| | | | | | | | | | Reviewers: aprantl, vsk, mattd, chandlerc Reviewed By: aprantl, vsk Differential Revision: https://reviews.llvm.org/D45657 llvm-svn: 330316
* [mips] Guard some macro expansions properlySimon Dardis2018-04-193-20/+24
| | | | | | | | Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D45565 llvm-svn: 330315
* [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers.Sander de Smalen2018-04-191-77/+69
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Renamed tryParseRegister to tryParseScalarRegister, which now returns an OperandMatchResultTy. - Moved matching of certain aliases into matchRegisterNameAlias. - Changed type of most 'Reg' variables to 'unsigned'. This is patch [1/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro, samparker Reviewed By: samparker Subscribers: samparker, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45687 llvm-svn: 330311
* [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs.Craig Topper2018-04-195-35/+81
| | | | | | This removes a bunch of unnecessary InstRW overrides. It also cleans up the missing information from the Sandy Bridge model. Other fixes to other models. llvm-svn: 330308
* Fix data race in X86FloatingPoint.cpp ASSERT_SORTEDBob Haarman2018-04-181-7/+8
| | | | | | | | | | | | | | | | | | | | | Summary: ASSERT_SORTED checks if a table is sorted, and uses a boolean to prevent the check from being run again if it was earlier determined that the table is in fact sorted. Unsynchronized reads and writes of that boolean triggered ThreadSanitizer's data race detection. This change rewrites the code to use std::atomic<bool> instead. Fixes PR36922. Reviewers: rnk Reviewed By: rnk Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D45742 llvm-svn: 330301
* [X86] Correct the Defs, Uses, hasSideEffects, mayLoad, mayStore for XCHG and ↵Craig Topper2018-04-183-35/+52
| | | | | | | | XADD instructions. I don't think we emit any of these from codegen except for using XCHG16ar as 2 byte NOP. llvm-svn: 330298
* [NVPTX, CUDA] Added support for m8n32k16 and m32n8k16 variants of wmma ↵Artem Belevich2018-04-184-17/+85
| | | | | | | | | | instructions. The new instructions were added added for sm_70+ GPUs in CUDA-9.1. Differential Revision: https://reviews.llvm.org/D45068 llvm-svn: 330296
* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-181-2/+3
| | | | | | | These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
* [X86] Fix the Uses/Defs,mayLoad,mayStore,hasSideEffects flags for the ↵Craig Topper2018-04-181-6/+13
| | | | | | | | CMPXCHG instructions. The compiler only emits the locked version of these which use different instruction definitions. The versions fixed here are only used by the assembler/disassembler. llvm-svn: 330287
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-189-266/+49
| | | | | | | | | Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
* [Power9]Legalize and emit code for converting Unsigned HWord/Char to ↵Lei Huang2018-04-181-0/+8
| | | | | | | | | | | | | | | | Quad-Precision Legalize and emit code for converting unsigned HWord/Char to QP: xscvsdqp xscvudqp Only covering patterns for unsigned forms cause we don't have part-word sign-extending integer loads into VSX registers. Differential Revision: https://reviews.llvm.org/D45494 llvm-svn: 330278
* [AArch64] Add isel pattern for v8i8->v2f32 NVCASTs.Amara Emerson2018-04-181-0/+1
| | | | | | rdar://39454635 llvm-svn: 330276
* [Power9]Legalize and emit code for converting (Un)Signed Word to Quad-PrecisionLei Huang2018-04-181-1/+10
| | | | | | | | | | | Legalize and emit code for converting (Un)Signed Word to quad-precision via: xscvsdqp xscvudqp Differential Revision: https://reviews.llvm.org/D45389 llvm-svn: 330273
* [DEBUG] Initial adaptation of NVPTX target for debug info emission.Alexey Bataev2018-04-1812-280/+222
| | | | | | | | | | | | | | | Summary: Patch adds initial emission of the debug info for NVPTX target. Currently, only .file and .loc directives are emitted, everything else is commented out to not break the compilation of Cuda. Reviewers: echristo, jlebar, tra, jholewinski Subscribers: mgorny, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41827 llvm-svn: 330271
* [x86] Switch EFLAGS copy lowering to use reg-reg form of testing forChandler Carruth2018-04-181-1/+1
| | | | | | | | | | | | | | | | a zero register. Previously I tried this and saw LLVM unable to transform this to fold with memory operands such as spill slot rematerialization. However, it clearly works as shown in this patch. We turn these into `cmpb $0, <mem>` when useful for folding a memory operand without issue. This form has no disadvantage compared to `testb $-1, <mem>`. So overall, this is likely no worse and may be slightly smaller in some cases due to the `testb %reg, %reg` form. Differential Revision: https://reviews.llvm.org/D45475 llvm-svn: 330269
* [support] Revert the changes made to Path.inc for the default Windows code pageAaron Smith2018-04-181-11/+5
| | | | | | | | | Path.inc/widenPath tries to decode the path using both UTF-8 and the default Windows code page. This is no longer necessary with the new InitLLVM method which ensures that the command line arguemnts are already UTF-8 on Windows. llvm-svn: 330266
* [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite usesChandler Carruth2018-04-181-82/+125
| | | | | | | | | | | | | | | | | | | | | | across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 llvm-svn: 330264
* [SimplifyLibcalls] Realloc(null, N) -> Malloc(N)Sanjay Patel2018-04-182-21/+46
| | | | | | | | Patch by Dávid Bolvanský! Differential Revision: https://reviews.llvm.org/D45413 llvm-svn: 330259
* [AMDGPU] Fix issues for backend divergence trackingDavid Stuttard2018-04-182-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A change to use divergence analysis in the AMDGPU backend was getting formal arguments incorrect (not tagged as divergent) unless they were VGPR0, VGPR1 or VGPR2 For graphics shaders it is possible to have more than these passed in as VGPR Modified the checking code to check for any VGPR registers passed in as formal arguments. Also, some intrinsics that are sources of divergence may have been lowered during instruction selection and are missed on subsequent calls to isSDNodeSourceOfDivergence - added the relevant AMDGPUISD checks as well. Finally, the FunctionLoweringInfo tracks virtual registers that are live across basic block boundaries. This is used to check for divergence of CopyFromRegister registers using the DivergenceAnalysis analysis. For multiple blocks the lazily evaluated inverted map VirtReg2Value was not cleared when the ValueMap map was. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45372 Change-Id: I112f3bd6dfe0f62e63ce9b43b893982778e4bee3 llvm-svn: 330257
* [IRCE] Only check for NSW on equality predicatesSam Parker2018-04-181-29/+14
| | | | | | | | | | | After investigation discussed in D45439, it would seem that the nsw flag restriction is unnecessary in most cases. So the IsInductionVar lambda has been removed, the functionality extracted, and now only require nsw when using eq/ne predicates. Differential Revision: https://reviews.llvm.org/D45617 llvm-svn: 330256
* [cmake] Improve pthread_[gs]etname_np detection codePavel Labath2018-04-181-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Due to some android peculiarities, in some build configurations (statically linked executables targeting older releases) we could detect the presence of these functions (because they are present in libc.a, where check_library_exists searches), but then fail to build because the headers did not include the definition. This attempts to remedy that by upgrading the check_library_exists to check_symbol_exists, which will check that the function is declared too. I am hoping that a more thorough check will make the messy #ifdef we have accumulated in the code obsolete, so I optimistically try to remove them. Reviewers: zturner, kparzysz, danalbert Subscribers: srhines, mgorny, krytarowski, llvm-commits Differential Revision: https://reviews.llvm.org/D45359 llvm-svn: 330251
* [LoopUnroll] Only peel if a predicate becomes known in the loop body.Florian Hahn2018-04-181-7/+25
| | | | | | | | | | | | | If a predicate does not become known after peeling, peeling is unlikely to be beneficial. Reviewers: mcrosier, efriedma, mkazantsev, junbuml Reviewed By: mkazantsev Differential Revision: https://reviews.llvm.org/D44983 llvm-svn: 330250
* [CodeGen/Dwarf] Make debug_names compatible with split-dwarfPavel Labath2018-04-183-7/+17
| | | | | | | | | | | | | | | | | | Summary: Previously we crashed for the combination of the two features because we tried to reference the dwo CU from the main object file. The fix consists of two items: - reference the skeleton CU from the name index (the consumer is expected to use the skeleton CU to find the real data). - use the main object file string pool for the strings in the index Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45566 llvm-svn: 330249
* [DebugInfo] Sink related dbg users when sinking in InstCombineBjorn Pettersson2018-04-181-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When sinking an instruction in InstCombine we now also sink the DbgInfoIntrinsics that are using the sunken value. Example) When sinking the load in this input bb.X: %0 = load i64, i64* %start, align 4, !dbg !31 tail call void @llvm.dbg.value(metadata i64 %0, ...) br i1 %cond, label %for.end, label %for.body.lr.ph for.body.lr.ph: br label %for.body we now also move the dbg.value, like this bb.X: br i1 %cond, label %for.end, label %for.body.lr.ph for.body.lr.ph: %0 = load i64, i64* %start, align 4, !dbg !31 tail call void @llvm.dbg.value(metadata i64 %0, ...) br label %for.body In the past we haven't moved the dbg.value so we got bb.X: tail call void @llvm.dbg.value(metadata i64 %0, ...) br i1 %cond, label %for.end, label %for.body.lr.ph for.body.lr.ph: %0 = load i64, i64* %start, align 4, !dbg !31 br label %for.body So in the past we got a debug-use before the def of %0. And that dbg.value was also on the path jumping to %for.end, for which %0 never was defined. CodeGenPrepare normally comes to rescue later (when not moving the dbg.value), since it moves dbg.value instrinsics quite brutally, without really analysing if it is correct to move the intrinsic (see PR31878). So at the moment this patch isn't expected to have much impact, besides that it is moving the dbg.value already in opt, making the IR look more sane directly. This can be seen as a preparation to (hopefully) make it possible to turn off CodeGenPrepare::placeDbgValues later as a solution to PR31878. I also adjusted test/DebugInfo/X86/sdagsplit-1.ll to make the IR in the test case up-to-date with this behavior in InstCombine. Reviewers: rnk, vsk, aprantl Reviewed By: vsk, aprantl Subscribers: mattd, JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D45425 llvm-svn: 330243
* [X86][Broadwell] Remove some unnecessary InstRW overrides and add some FIXMEs.Craig Topper2018-04-181-43/+8
| | | | llvm-svn: 330241
* [X86] Give CMOV 2 cycle latency on SLM.Craig Topper2018-04-181-1/+1
| | | | llvm-svn: 330239
* [X86] Don't crash on bad operand modifiers in inline assemblyCraig Topper2018-04-181-0/+6
| | | | | | | | | | | | | | Summary: Previously if a modifer was placed on a non-GPR register class we would hit an assert or crash. Reviewers: echristo Reviewed By: echristo Subscribers: eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D45751 llvm-svn: 330238
* [InstCombine] peek through bitcasted vector/array pointer GEP operandSanjay Patel2018-04-181-5/+25
| | | | | | | | | | | | | | The bitcast may be interfering with other combines or vectorization as shown in PR16739: https://bugs.llvm.org/show_bug.cgi?id=16739 Most pointer-related optimizations are probably able to look through this bitcast, but removing the bitcast shrinks the IR, so it's at least a size savings. Differential Revision: https://reviews.llvm.org/D44833 llvm-svn: 330237
* Fix lock order inversion between ManagedStatic and StatisticBob Haarman2018-04-171-2/+13
| | | | | | | | | | | | | | | | | | | | | Summary: Statistic and ManagedStatic both use mutexes. There was a lock order inversion where, during initialization, Statistic's mutex would be held while taking ManagedStatic's, and in llvm_shutdown, ManagedStatic's mutex would be held while taking Statistic's mutex. This change causes Statistic's initialization code to avoid holding its mutex while calling ManagedStatic's methods, avoiding the inversion. Reviewers: dsanders, rtereshin Reviewed By: dsanders Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45398 llvm-svn: 330236
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-172-8/+19
| | | | | | | | Literal encoding needs op_sel_hi to select low 16 bit in this case. Differential Revision: https://reviews.llvm.org/D45745 llvm-svn: 330230
* [Mem2Reg] Create merged debug locations for inserted phisVedant Kumar2018-04-171-6/+32
| | | | | | | | | | | | | | | | | | | | | | Track the debug locations of the incoming values to newly-created phis, and apply merged debug locations to the phis. A merged location will be on line 0, but will have the correct scope set. This improves crash reporting when an inlined instruction with a merged location triggers a machine exception. A debugger will be able to narrow down the crash to the correct inlined scope, instead of simply pointing to the outer scope of the caller. Taken together with a change allows generating merged line-0 locations for instructions which aren't calls, this results in a 0.5% increase in the uncompressed size of the .debug_line section of a stage2+Release build of clang (-O3 -g). rdar://33858697 Differential Revision: https://reviews.llvm.org/D45397 llvm-svn: 330227
* [Mem2Reg] Make RenamePassData a struct, NFCVedant Kumar2018-04-171-3/+2
| | | | llvm-svn: 330226
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-179-49/+266
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* LoadStoreVectorizer crashes due to unsized typeStanislav Mekhanoshin2018-04-171-2/+4
| | | | | | | | | When we skip bitcasts while looking for GEP in LoadSoreVectorizer we should also verify that the type is sized otherwise we assert Differential Revision: https://reviews.llvm.org/D45709 llvm-svn: 330221
* [XRay] Typed event logging intrinsicKeith Wyss2018-04-176-352/+984
| | | | | | | | | | | | | | | | | | | | | Summary: Add an LLVM intrinsic for type discriminated event logging with XRay. Similar to the existing intrinsic for custom events, but also accepts a type tag argument to allow plugins to be aware of different types and semantically interpret logged events they know about without choking on those they don't. Relies on a symbol defined in compiler-rt patch D43668. I may wait to submit before I can see demo everything working together including a still to come clang patch. Reviewers: dberris, pelikan, eizan, rSerge, timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45633 llvm-svn: 330219
* [WebAssembly] Add an assertion for an invalid CFGHeejin Ahn2018-04-171-0/+3
| | | | | | | | | | | | | | | Summary: It was not easy to provide a test case for D45648 (rL330079) because the bug didn't manifest itself in the set of currently valid IRs. Added an assertion to check this faster, thanks to @dblaikie's suggestion. Reviewers: dblaikie Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits, dblaikie Differential Revision: https://reviews.llvm.org/D45711 llvm-svn: 330217
* Rename sys::Process::GetArgumentVector -> sys::windows::GetCommandLineArgumentsRui Ueyama2018-04-174-40/+39
| | | | | | | | | | | | | | GetArgumentVector (or GetCommandLineArguments) is very Windows-specific. I think it doesn't make much sense to provide that function from sys::Process. I also made a change so that the function takes a BumpPtrAllocator instead of a SpecificBumpPtrAllocator. The latter is the class to call dtors, but since char * is trivially destructible, we should use the former class. Differential Revision: https://reviews.llvm.org/D45641 llvm-svn: 330216
* [WebAssembly] Teach fast-isel to gracefully recover from illegal return types.Dan Gohman2018-04-171-2/+6
| | | | | | Fixes PR36564. llvm-svn: 330215
* [llvm-pdbutil] Dump first section contribution for each module.Zachary Turner2018-04-172-1/+5
| | | | | | | | | | | | | | The DBI stream contains a list of module descriptors. At the beginning of each descriptor is a structure representing the first section contribution in the output file for that module. LLD currently doesn't fill out this structure at all, but link.exe does. So as a precursor to emitting this data in LLD, we first need a way to dump it so that it can be checked. This patch adds support for the dumping, and verifies via a test that LLD emits bogus information. llvm-svn: 330208
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-1713-22/+18
| | | | llvm-svn: 330204
* [X86] Remove unnecessary InstRW overrides. Add somes FIXMEs/TODOs.Craig Topper2018-04-175-98/+17
| | | | llvm-svn: 330203
* [Hexagon] Do not merge initializers for stack and non-stack expressionsKrzysztof Parzyszek2018-04-171-2/+42
| | | | | | | | | Stack addressing needs addressing modes that provide an offset field immediately following the frame index. An initializer from a non-stack addressing could force the stack address to use a form that does not provide an offset field. llvm-svn: 330191
* [LLVM-C] [PR34633] Avoid calling ->dump() methods from LLVMDump*.whitequark2018-04-171-5/+3
| | | | | | | | | | LLVMDump* functions are available in Release builds too. Patch by Brenton Bostick. Differential Revision: https://reviews.llvm.org/D44600 llvm-svn: 330189
* Fix incorrect choice of callee-saved registers save/restore pointsMomchil Velikov2018-04-171-2/+14
| | | | | | | | Make the shrink wrapping pass pay attention to uses/defs of the stack pointer. Differential revision: https://reviews.llvm.org/D45524 llvm-svn: 330183
* Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." again."Michael Zolotukhin2018-04-171-22/+15
| | | | | | This reverts r330175. There are still stage3/stage4 miscompares. llvm-svn: 330180
* [X86] Add FP comparison scheduler classesSimon Pilgrim2018-04-1713-315/+105
| | | | | | | | Split VCMP/VMAX/VMIN instructions off to WriteFCmp and VCOMIS instructions off to WriteFCom instead of assuming they match WriteFAdd Differential Revision: https://reviews.llvm.org/D45656 llvm-svn: 330179
* [DAGCombiner] Fix for oss-fuzz bugGerolf Hoflehner2018-04-171-1/+2
| | | | llvm-svn: 330178
OpenPOWER on IntegriCloud