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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-19 11:16:33 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-19 11:16:33 +0000 |
| commit | 33dede90759152fd9632c821ef4e6d039170fe1e (patch) | |
| tree | c8862e16dc09514e89367e3cb004ab19788deb12 /llvm/lib | |
| parent | b04cd1b9f3a877290d893c9a19ea3ea40e38a135 (diff) | |
| download | bcm5719-llvm-33dede90759152fd9632c821ef4e6d039170fe1e.tar.gz bcm5719-llvm-33dede90759152fd9632c821ef4e6d039170fe1e.zip | |
[X86][BtVer2] Remove 128-bit F16C InstRW overrides.
These are already handled identically by WriteCvtF2F.
llvm-svn: 330318
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 694d7047c0a..2fc33354fa1 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -502,21 +502,11 @@ def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>; // F16C instructions. //////////////////////////////////////////////////////////////////////////////// -def JWriteCVT3: SchedWriteRes<[JFPU1, JSTC]> { - let Latency = 3; -} -def : InstRW<[JWriteCVT3], (instrs VCVTPS2PHrr, VCVTPH2PSrr)>; - def JWriteCVT3St: SchedWriteRes<[JFPU1, JSTC, JSAGU]> { let Latency = 3; } def : InstRW<[JWriteCVT3St], (instrs VCVTPS2PHmr)>; -def JWriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1, JSTC]> { - let Latency = 8; -} -def : InstRW<[JWriteCVT3Ld], (instrs VCVTPH2PSrm)>; - def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JSTC, JFPX]> { let Latency = 6; let ResourceCycles = [2, 2, 2]; |
