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| author | Lei Huang <lei@ca.ibm.com> | 2018-04-18 16:34:22 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-04-18 16:34:22 +0000 |
| commit | 198e67857645aa25164aead779d18d65bb75a510 (patch) | |
| tree | fd3c86fd5d3364ab197f55bfec31b5944ae90a01 /llvm/lib | |
| parent | e36c67b35c26d7c9a2974ffd2f8ba6a9f0260f15 (diff) | |
| download | bcm5719-llvm-198e67857645aa25164aead779d18d65bb75a510.tar.gz bcm5719-llvm-198e67857645aa25164aead779d18d65bb75a510.zip | |
[Power9]Legalize and emit code for converting (Un)Signed Word to Quad-Precision
Legalize and emit code for converting (Un)Signed Word to quad-precision via:
xscvsdqp
xscvudqp
Differential Revision: https://reviews.llvm.org/D45389
llvm-svn: 330273
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index d84f828949e..1fb020b3876 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2514,11 +2514,20 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>; def : Pat<(f128 (sint_to_fp i64:$src)), (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; - def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>; def : Pat<(f128 (uint_to_fp i64:$src)), (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; + // Convert (Un)Signed Word -> QP + def : Pat<(f128 (sint_to_fp i32:$src)), + (f128 (XSCVSDQP (MTVSRWA $src)))>; + def : Pat<(f128 (sint_to_fp (i32 (load xoaddr:$src)))), + (f128 (XSCVSDQP (LIWAX xoaddr:$src)))>; + def : Pat<(f128 (uint_to_fp i32:$src)), + (f128 (XSCVUDQP (MTVSRWZ $src)))>; + def : Pat<(f128 (uint_to_fp (i32 (load xoaddr:$src)))), + (f128 (XSCVUDQP (LIWZX xoaddr:$src)))>; + let UseVSXReg = 1 in { //===--------------------------------------------------------------------===// // Round to Floating-Point Integer Instructions |
