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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2018-04-17 23:09:05 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2018-04-17 23:09:05 +0000 |
| commit | 8b20b7dc2bb9b995d94ab020eaaf2d488d935628 (patch) | |
| tree | 78a2345c542b81b659d5fe81579b1583373ccf71 /llvm/lib | |
| parent | 4b9b9fb7a0a203e705455a521fef3e16f18e1c4f (diff) | |
| download | bcm5719-llvm-8b20b7dc2bb9b995d94ab020eaaf2d488d935628.tar.gz bcm5719-llvm-8b20b7dc2bb9b995d94ab020eaaf2d488d935628.zip | |
[AMDGPU] Enabled v2.16 literals for VOP3P
Literal encoding needs op_sel_hi to select low 16 bit in this case.
Differential Revision: https://reviews.llvm.org/D45745
llvm-svn: 330230
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 8 |
2 files changed, 19 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 67f64894270..be98720765e 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -155,6 +155,25 @@ static bool updateOperand(FoldCandidate &Fold, assert(Old.isReg()); if (Fold.isImm()) { + if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked) { + // Set op_sel_hi on this operand or bail out if op_sel is already set. + unsigned Opcode = MI->getOpcode(); + int OpNo = MI->getOperandNo(&Old); + int ModIdx = -1; + if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) + ModIdx = AMDGPU::OpName::src0_modifiers; + else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) + ModIdx = AMDGPU::OpName::src1_modifiers; + else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2)) + ModIdx = AMDGPU::OpName::src2_modifiers; + assert(ModIdx != -1); + ModIdx = AMDGPU::getNamedOperandIdx(Opcode, ModIdx); + MachineOperand &Mod = MI->getOperand(ModIdx); + unsigned Val = Mod.getImm(); + if ((Val & SISrcMods::OP_SEL_0) || !(Val & SISrcMods::OP_SEL_1)) + return false; + Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1); + } Old.ChangeToImmediate(Fold.ImmToFold); return true; } diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 02efecf2631..706f0171dbd 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -97,11 +97,6 @@ unsigned getVmcntBitWidthHi() { return 2; } namespace llvm { -static cl::opt<bool> EnablePackedInlinableLiterals( - "enable-packed-inlinable-literals", - cl::desc("Enable packed inlinable literals (v2f16, v2i16)"), - cl::init(false)); - namespace AMDGPU { LLVM_READNONE @@ -877,9 +872,6 @@ bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) { bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) { assert(HasInv2Pi); - if (!EnablePackedInlinableLiterals) - return false; - int16_t Lo16 = static_cast<int16_t>(Literal); int16_t Hi16 = static_cast<int16_t>(Literal >> 16); return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi); |
