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* [Constants] Simplify type checking switch in ConstantExpr::get.Craig Topper2019-05-051-26/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: Remove duplicate checks that both operands have the same type. This is checked before the switch. Use 'integer' or 'floating-point' instead of 'arithmetic' type. I think this might be a leftover to the days when floating point and integer operations shared the same opcodes. Reviewers: spatel, RKSimon, dblaikie Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61558 llvm-svn: 359985
* [MCA] Notify event listeners when instructions transition to the Pending ↵Andrea Di Biagio2019-05-052-8/+35
| | | | | | state. NFCI llvm-svn: 359983
* Add FNeg IR constant folding supportCameron McInally2019-05-054-5/+63
| | | | llvm-svn: 359982
* [X86] Make X86RegisterInfo(const Triple &TT) constructor explicit.Simon Pilgrim2019-05-051-1/+1
| | | | | | Fixes cppcheck warning. llvm-svn: 359981
* [X86] Fix some cppcheck "Local variable name shadows outer variable" ↵Simon Pilgrim2019-05-051-44/+42
| | | | | | warnings. NFCI. llvm-svn: 359976
* [SLPVectorizer] Make getSpillCost() const. NFCI.Simon Pilgrim2019-05-051-2/+9
| | | | | | Ideally getTreeCost() should be const as well but non-const Type creation would need to be addressed first. llvm-svn: 359975
* [SelectionDAG] Use any_of/all_of where possible. NFCI.Simon Pilgrim2019-05-051-14/+4
| | | | llvm-svn: 359974
* Move Value *RHSCIOp def into the scope where its actually used. NFCI.Simon Pilgrim2019-05-051-2/+1
| | | | llvm-svn: 359973
* [CodeGenPrepare] limit overflow intrinsic matching to a single basic block ↵Sanjay Patel2019-05-041-28/+21
| | | | | | | | | | | | | | | | | | | | | (2nd try) This is a subset of the original commit from rL359879 which was reverted because it could crash when using the 'RemovedInstructions' structure that enables delayed deletion of dead instructions. The motivating compile-time win does not require that change though. We should get most of that win from this change alone. Using/updating a dominator tree to match math overflow patterns may be very expensive in compile-time (because of the way CGP uses a DT), so just handle the single-block case. See post-commit thread for rL354298 for more details: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190422/646276.html Differential Revision: https://reviews.llvm.org/D61075 llvm-svn: 359969
* [AMDGPU] Fixed asan error after D61536Stanislav Mekhanoshin2019-05-041-1/+1
| | | | llvm-svn: 359963
* AMDGPU] gfx1010 hazard recognizerStanislav Mekhanoshin2019-05-042-3/+268
| | | | | | Differential Revision: https://reviews.llvm.org/D61536 llvm-svn: 359961
* [AMDGPU] gfx1010: use fmac instructionsStanislav Mekhanoshin2019-05-044-39/+105
| | | | | | Differential Revision: https://reviews.llvm.org/D61527 llvm-svn: 359959
* [JITLink] Add two useful Section operations: find by name, get address range.Lang Hames2019-05-041-9/+2
| | | | | | | | These operations were already used in eh-frame registration, and are likely to be used in other runtime registrations, so this commit moves them into a header where they can be re-used. llvm-svn: 359950
* [AArch64][GlobalISel] Use fcsel instead of csel for G_SELECT on FPRsJessica Paquette2019-05-032-24/+75
| | | | | | | | | | | | | | | | | | | | | | | | This saves us some unnecessary copies. If the inputs to a G_SELECT are floating point, we should use fcsel rather than csel. Changes here are... - Teach selectCopy about s1-to-s1 copies across register banks. - AArch64RegisterBankInfo about G_SELECT in general. - Teach the instruction selector about the FCSEL instructions. Also add two tests: - select-select.mir to show that we get the expected FCSEL - regbank-select.mir (unfortunately named) to show the register banks on G_SELECT are properly preserved And update fast-isel-select.ll to show that we do the same thing as other instruction selectors in these cases. llvm-svn: 359940
* [AMDGPU] gfx1010 wait count insertionStanislav Mekhanoshin2019-05-031-56/+144
| | | | | | Differential Revision: https://reviews.llvm.org/D61534 llvm-svn: 359938
* [AMDGPU] gfx1010 s_code_end generationStanislav Mekhanoshin2019-05-034-2/+45
| | | | | | | | Also add some missing metadata in the streamer. Differential Revision: https://reviews.llvm.org/D61531 llvm-svn: 359937
* [AMDGPU] gfx1010 loop alignmentStanislav Mekhanoshin2019-05-032-0/+78
| | | | | | Differential Revision: https://reviews.llvm.org/D61529 llvm-svn: 359935
* [COFF, ARM64] Fix ABI implementation of struct returnsMandeep Singh Grang2019-05-034-2/+80
| | | | | | | | | | | | | | | | | | | Summary: Refer the ABI doc at: https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019#return-values Related clang patch: D60349 Reviewers: rnk, efriedma, TomTan, ssijaric Reviewed By: rnk, efriedma Subscribers: mstorsjo, javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60348 llvm-svn: 359934
* Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out ↵Matt Arsenault2019-05-031-4/+41
| | | | | | | | | | | of a block" This reverts commit r359912. This should pass now, since the clang test was made less fragile in r359918. llvm-svn: 359919
* [CommandLine] Enable Grouping for short options by default. Part 4 of 5Don Hinton2019-05-031-0/+2
| | | | | | | | | | | | | | | | | | | Summary: This change enables `cl::Grouping` for short options -- options with names of a single character. This is consistent with GNU getopt behavior. Reviewers: rnk, MaskRay Reviewed By: MaskRay Subscribers: thopre, cfe-commits, MaskRay, rupprecht, hiraditya, llvm-commits Tags: #llvm, #clang Differential Revision: https://reviews.llvm.org/D61270 llvm-svn: 359917
* [DAGCombine] Remove repeated variables. NFCI.Simon Pilgrim2019-05-031-8/+3
| | | | llvm-svn: 359915
* Revert r359906, "RegAllocFast: Add heuristic to detect values not live-out ↵Nico Weber2019-05-031-41/+4
| | | | | | | | of a block" Makes clang/test/Misc/backend-stack-frame-diagnostics-fallback.cpp fail. llvm-svn: 359912
* [TargetLowering] SimplifySetCC - remove repeated variable. NFCI.Simon Pilgrim2019-05-031-2/+1
| | | | | | Also reduce scope of Temp variable. llvm-svn: 359911
* [CommandLine] Change help output to prefix long options with `--` instead of ↵Don Hinton2019-05-031-34/+63
| | | | | | | | | | | | | | | | | | | | | | | | `-`. NFC . Part 3 of 5 Summary: By default, `parseCommandLineOptions()` will accept either a `-` or `--` prefix for long options -- options with names longer than a single character. While this change does not affect behavior, it will be helpful with a subsequent change that requires long options use the `--` prefix. Reviewers: rnk, thopre Reviewed By: thopre Subscribers: thopre, cfe-commits, hiraditya, llvm-commits Tags: #llvm, #clang Differential Revision: https://reviews.llvm.org/D61269 llvm-svn: 359909
* Revert "[CodeGenPrepare] limit overflow intrinsic matching to a single basic ↵Evgeniy Stepanov2019-05-031-42/+47
| | | | | | | | block" This reverts commit r359879, which introduced a compiler crash. llvm-svn: 359908
* RegAllocFast: Add heuristic to detect values not live-out of a blockMatt Arsenault2019-05-031-4/+41
| | | | | | | | | Add an improved/new heuristic to catch more cases when values are not live out of a basic block. Patch by Matthias Braun llvm-svn: 359906
* [hexagon] change AsmParser assertion to errorBrian Cain2019-05-031-10/+10
| | | | | | | For immediates that can't be evaluated in assembler-mapped instructions, we should return 'invalid operand' instead of assert. llvm-svn: 359905
* [X86] Allow assembly parser to accept x/y/z suffixes on non-memory ↵Craig Topper2019-05-031-5/+26
| | | | | | | | | | | | vfpclassps/pd and on memory forms in intel syntax The x/y/z suffix is needed to disambiguate the memory form in at&t syntax since no xmm/ymm/zmm register is mentioned. But we should also allow it for the register and broadcast forms where its not needed for consistency. This matches gas. The printing code will still only use the suffix for the memory form where it is needed. llvm-svn: 359903
* [X86] LowerToHorizontalOp - Tidyup calls to getHopForBuildVector. NFCI.Simon Pilgrim2019-05-031-15/+7
| | | | | | Merge the if() tests for the various HADD/SUB + Subtarget tests llvm-svn: 359901
* [SelectionDAG] CreateTopologicalOrder - don't use iteratorSimon Pilgrim2019-05-031-10/+6
| | | | | | | | We shouldn't use an iterator to loop across a std::vector when the same loop is adding elements to that std::vector Found by cppcheck llvm-svn: 359900
* AMDGPU: Select VOP3 form of subMatt Arsenault2019-05-031-2/+2
| | | | | | | | | | The VOP3 form should always be the preferred selection form to be shrunk later. The r600 sub test needs to be split out because it asserts on the arguments in the new test during the calling convention lowering. llvm-svn: 359899
* AMDGPU: Support shrinking add with FI in SIFoldOperandsMatt Arsenault2019-05-031-35/+37
| | | | | | Avoids test regression in a future patch llvm-svn: 359898
* AMDGPU: Remove redundant patterns for shiftsMatt Arsenault2019-05-031-9/+4
| | | | llvm-svn: 359895
* AMDGPU: Remove redundant patterns for subMatt Arsenault2019-05-031-4/+0
| | | | | | | There were 2 patterns for sub, one selecting to sub and one to subrev. Only one of these will succeed, so remove the reversed one. llvm-svn: 359894
* AMDGPU: Replace shrunk instruction with dummy implicit_defMatt Arsenault2019-05-031-4/+8
| | | | | | | | | | | | This was broken if the original operand was killed. The kill flag would appear on both instructions, and fail the verifier. Keep the kill flag, but remove the operands from the old instruction. This has an added benefit of really reducing the use count for future folds. Ideally the pass would be structured more like what PeepholeOptimizer does to avoid this hack to avoid breaking instruction iterators. llvm-svn: 359891
* [TargetLowering] ShrinkDemandedConstant - reduce scope of TLO.DAG variable. ↵Simon Pilgrim2019-05-031-3/+2
| | | | | | | | NFCI. Only ever used in one block llvm-svn: 359890
* [X86] Remove repeated variables. NFCI.Simon Pilgrim2019-05-031-2/+0
| | | | llvm-svn: 359889
* Avoid cppcheck operator precedence warnings. NFCI.Simon Pilgrim2019-05-035-6/+6
| | | | | | Prefer ((X & Y) ? A : B) to (X & Y ? A : B) llvm-svn: 359884
* AMDGPU: Fix incorrect commute with sub when folding immediatesMatt Arsenault2019-05-031-1/+4
| | | | | | | | | When a fold of an immediate into a sub/subrev required shrinking the instruction, the wrong VOP2 opcode was used. This was using the VOP2 equivalent of the original instruction, not the commuted instruction with the inverted opcode. llvm-svn: 359883
* [CodeGenPrepare] limit overflow intrinsic matching to a single basic blockSanjay Patel2019-05-031-47/+42
| | | | | | | | | | | | | | | | | | | Using/updating a dominator tree to match math overflow patterns may be very expensive in compile-time (because of the way CGP uses a DT), so just handle the single-block case. Also, we were restarting the iterator loops when doing the overflow intrinsic transforms by marking the dominator tree for update. That was done to prevent iterating over a removed instruction. But we can postpone the deletion using the existing "RemovedInsts" structure, and that means we don't need to update the DT. See post-commit thread for rL354298 for more details: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190422/646276.html Differential Revision: https://reviews.llvm.org/D61075 llvm-svn: 359879
* [Object][XCOFF] Add an XCOFF dumper for llvm-readobj.Sean Fertile2019-05-031-7/+34
| | | | | | | | | | | Patch adds support for dumping of file headers with llvm-readobj. XCOFF object files are added to test dumping a well formed file, and dumping both negative timestamps and negative symbol counts, both of which are allowed in the XCOFF definition. Differential Revision: https://reviews.llvm.org/D60878 llvm-svn: 359878
* [TargetLowering] expandUnalignedStore - cleanup EVT variables. NFCI.Simon Pilgrim2019-05-031-23/+18
| | | | | | Avoid duplicated EVTs and rename Store/Load VTs to avoid -Wshadow warnings. llvm-svn: 359877
* Revert "[MIR] Add simple PRE pass to MachineCSE"Anton Afanasyev2019-05-031-117/+9
| | | | | | | This reverts commit 9c20156de39b377190d7a91783d61877b303fe35. It breaks stage 2 of clang-ppc64be-linux-multistage. llvm-svn: 359875
* [SelectionDAG] Use INT_MIN as (1 << 31) is UB for signed integers. NFCI.Simon Pilgrim2019-05-031-2/+2
| | | | llvm-svn: 359873
* [SelectionDAG] computeKnownBits - remove some duplicate/shadow variables. NFCI.Simon Pilgrim2019-05-031-6/+4
| | | | llvm-svn: 359872
* [X86] LowerMULH - remove unused Lo/Hi vector indices. NFCI.Simon Pilgrim2019-05-031-5/+2
| | | | | | Leftover from before we had the extract128BitVector helpers. llvm-svn: 359871
* [MIR] Add simple PRE pass to MachineCSEAnton Afanasyev2019-05-031-9/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 Reviewers: RKSimon Subscribers: hfinkel, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56772 llvm-svn: 359870
* Reduce variable scope to just the if() block its actually used in. NFCI.Simon Pilgrim2019-05-031-2/+1
| | | | llvm-svn: 359869
* [X86] Add more one checks to masked compare patterns that were missed in ↵Craig Topper2019-05-031-46/+48
| | | | | | | | | r358358. This covers the patterns we use for widening 128/256 comparisons to 512-bit when AVX512VL isn't supported. llvm-svn: 359863
* [IRTranslator] Use the alloc size instead of the store size when translating ↵Quentin Colombet2019-05-031-1/+1
| | | | | | | | | | | | | | allocas We use to incorrectly use the store size instead of the alloc size when creating the stack slot for allocas. On aarch64 this can be demonstrated by allocating weirdly sized types. For instance, in the added test case, we use an alloca for i19. We used to allocate a slot of size 24-bit (19 rounded up to the next byte), whereas we really want to use a full 32-bit slot for this type. llvm-svn: 359856
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