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| author | Craig Topper <craig.topper@intel.com> | 2019-05-03 16:15:15 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-05-03 16:15:15 +0000 |
| commit | a8f3840c62a7c0fde28e9a3f1a32e30ba5579121 (patch) | |
| tree | fd5a0a439fbaed10529aa3ec68e51098af5933b2 /llvm/lib | |
| parent | 9bc070077efba53728de05769b803258f832b0d8 (diff) | |
| download | bcm5719-llvm-a8f3840c62a7c0fde28e9a3f1a32e30ba5579121.tar.gz bcm5719-llvm-a8f3840c62a7c0fde28e9a3f1a32e30ba5579121.zip | |
[X86] Allow assembly parser to accept x/y/z suffixes on non-memory vfpclassps/pd and on memory forms in intel syntax
The x/y/z suffix is needed to disambiguate the memory form in at&t syntax since no xmm/ymm/zmm register is mentioned.
But we should also allow it for the register and broadcast forms where its not needed for consistency. This matches gas.
The printing code will still only use the suffix for the memory form where it is needed.
llvm-svn: 359903
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index b397ccd1dd9..d857b8ef1dc 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2669,7 +2669,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, EVEX_K, Sched<[sched]>; def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst), (ins _.MemOp:$src1, i32u8imm:$src2), - OpcodeStr##_.Suffix##mem# + OpcodeStr##_.Suffix#"{"#mem#"}"# "\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.KRC:$dst,(X86Vfpclass (_.VT (_.LdFrag addr:$src1)), @@ -2677,7 +2677,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, Sched<[sched.Folded, sched.ReadAfterFold]>; def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2), - OpcodeStr##_.Suffix##mem# + OpcodeStr##_.Suffix#"{"#mem#"}"# "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", [(set _.KRC:$dst, (and _.KRCWM:$mask, (X86Vfpclass_su (_.VT (_.LdFrag addr:$src1)), @@ -2704,6 +2704,27 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, (i32 imm:$src2))))]>, EVEX_B, EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>; } + + // Allow registers or broadcast with the x, y, z suffix we use to disambiguate + // the memory form. + def : InstAlias<OpcodeStr#_.Suffix#mem# + "\t{$src2, $src1, $dst|$dst, $src1, $src2}", + (!cast<Instruction>(NAME#"rr") + _.KRC:$dst, _.RC:$src1, i32u8imm:$src2), 0, "att">; + def : InstAlias<OpcodeStr#_.Suffix#mem# + "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", + (!cast<Instruction>(NAME#"rrk") + _.KRC:$dst, _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2), 0, "att">; + def : InstAlias<OpcodeStr#_.Suffix#mem# + "\t{$src2, ${src1}"#_.BroadcastStr#", $dst|$dst, ${src1}"# + _.BroadcastStr#", $src2}", + (!cast<Instruction>(NAME#"rmb") + _.KRC:$dst, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">; + def : InstAlias<OpcodeStr#_.Suffix#mem# + "\t{$src2, ${src1}"#_.BroadcastStr#", $dst {${mask}}|" + "$dst {${mask}}, ${src1}"#_.BroadcastStr#", $src2}", + (!cast<Instruction>(NAME#"rmbk") + _.KRC:$dst, _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">; } multiclass avx512_vector_fpclass_all<string OpcodeStr, AVX512VLVectorVTInfo _, @@ -2711,13 +2732,13 @@ multiclass avx512_vector_fpclass_all<string OpcodeStr, AVX512VLVectorVTInfo _, Predicate prd>{ let Predicates = [prd] in { defm Z : avx512_vector_fpclass<opc, OpcodeStr, sched.ZMM, - _.info512, "{z}">, EVEX_V512; + _.info512, "z">, EVEX_V512; } let Predicates = [prd, HasVLX] in { defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, sched.XMM, - _.info128, "{x}">, EVEX_V128; + _.info128, "x">, EVEX_V128; defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, sched.YMM, - _.info256, "{y}">, EVEX_V256; + _.info256, "y">, EVEX_V256; } } |
