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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-03 15:08:35 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-03 15:08:35 +0000 |
| commit | ada33314a298dc84636af8337eaa77d259d46fcf (patch) | |
| tree | 04bacf332b8691249809ef9d4c739861e90c4425 /llvm/lib | |
| parent | ca7a582bf3bcbc233a13761ea2b56fe658debd6a (diff) | |
| download | bcm5719-llvm-ada33314a298dc84636af8337eaa77d259d46fcf.tar.gz bcm5719-llvm-ada33314a298dc84636af8337eaa77d259d46fcf.zip | |
AMDGPU: Remove redundant patterns for sub
There were 2 patterns for sub, one selecting to sub and one to
subrev. Only one of these will succeed, so remove the reversed one.
llvm-svn: 359894
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index db7a567d014..33b4cb774a5 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -528,16 +528,12 @@ let AddedComplexity = 1 in { let SubtargetPredicate = HasAddNoCarryInsts in { def : DivergentBinOp<add, V_ADD_U32_e32>; def : DivergentBinOp<sub, V_SUB_U32_e32>; - def : DivergentBinOp<sub, V_SUBREV_U32_e32>; } let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in { def : DivergentBinOp<add, V_ADD_I32_e32>; - def : DivergentBinOp<sub, V_SUB_I32_e32>; -def : DivergentBinOp<sub, V_SUBREV_I32_e32>; - def : DivergentBinOp<srl, V_LSHRREV_B32_e32>; def : DivergentBinOp<sra, V_ASHRREV_I32_e32>; def : DivergentBinOp<shl, V_LSHLREV_B32_e32>; |
