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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-15 02:25:28 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-15 02:25:28 +0000 |
| commit | c79dc70d500f0615b5543f0c73715aed07610d7a (patch) | |
| tree | 7d6c2b48272b9244b8d68586b2c02d7a9d6cf243 /llvm/lib | |
| parent | 79d7f70dfd54d4b3c8cd8dbeba77e2474ef9d6c9 (diff) | |
| download | bcm5719-llvm-c79dc70d500f0615b5543f0c73715aed07610d7a.tar.gz bcm5719-llvm-c79dc70d500f0615b5543f0c73715aed07610d7a.zip | |
AMDGPU: Fix f16 fabs/fneg
llvm-svn: 286931
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 15 |
2 files changed, 18 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 56a0540a070..b4a7a65386d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -558,13 +558,12 @@ bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const { bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const { assert(VT.isFloatingPoint()); - return VT == MVT::f32 || VT == MVT::f64; + return VT == MVT::f32 || VT == MVT::f64 || (Subtarget->has16BitInsts() && + VT == MVT::f16); } bool AMDGPUTargetLowering::isFNegFree(EVT VT) const { - assert(VT.isFloatingPoint()); - return VT == MVT::f32 || VT == MVT::f64 || (Subtarget->has16BitInsts() && - VT == MVT::f16); + return isFAbsFree(VT); } bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT, diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 0905df9cd43..15f3ac55faf 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -665,6 +665,21 @@ def : Pat < sub1) >; +def : Pat < + (fneg f16:$src), + (V_XOR_B32_e32 $src, (V_MOV_B32_e32 (i32 0x00008000))) +>; + +def : Pat < + (fabs f16:$src), + (V_AND_B32_e64 $src, (V_MOV_B32_e32 (i32 0x00007fff))) +>; + +def : Pat < + (fneg (fabs f16:$src)), + (S_OR_B32 $src, (S_MOV_B32 (i32 0x00008000))) // Set sign bit +>; + /********** ================== **********/ /********** Immediate Patterns **********/ /********** ================== **********/ |
