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* Fix APFloat mod (committing for simonbyrne)Stephen Canon2017-03-311-33/+9
| | | | | | | | The previous version was prone to intermediate rounding or overflow. Differential Revision: https://reviews.llvm.org/D29346 llvm-svn: 299256
* [DAGCombiner] add fold for 'All sign bits set?'Sanjay Patel2017-03-311-2/+4
| | | | | | | | | | (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0) We have 7 similar folds, but this one got away. The fact that the x86 test with a branch didn't change is probably a separate bug. We may also be missing this and the related folds in instcombine. llvm-svn: 299252
* [AMDGPU] Remove assumption that vector and scalar types do not aliasStanislav Mekhanoshin2017-03-311-8/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D31547 llvm-svn: 299250
* [APInt] Remove shift functions from APIntOps namespace. Replace the few ↵Craig Topper2017-03-312-9/+9
| | | | | | users with the APInt class methods. NFCI llvm-svn: 299248
* Do not translate rint into nearbyint, but truncate it like nearbyint.Joerg Sonnenberger2017-03-312-1/+3
| | | | | | | | | | | | | | A common way to implement nearbyint is by fiddling with the floating point environment and calling rint. This is used at least by the BSD libm and musl. As such, canonicalizing the latter to the former will create infinite loops for libm and generally pessimize performance, at least when the generic C versions are used. This change preserves the rint in the libcall translation and also handles the domain truncation logic, so that rint with float argument will be reduced to rintf etc. llvm-svn: 299247
* AMDGPU: Remove unnecessary ands when f16 is legalMatt Arsenault2017-03-316-2/+57
| | | | | | | | | | Add a new node to act as a fancy bitcast from f16 operations to i32 that implicitly zero the high 16-bits of the result. Alternatively could try making v2f16 legal and canonicalizing on build_vectors. llvm-svn: 299246
* AMDGPU/R600: Fix amdgpu alias analysis pass.Jan Vesely2017-03-312-5/+11
| | | | | | | | | R600 uses higher AS number to access kernel parameters Fixes: r298846 Differential Revision: https://reviews.llvm.org/D31520 llvm-svn: 299245
* [APInt] Rewrite getLoBits in a way that will do one less memory allocation ↵Craig Topper2017-03-311-3/+4
| | | | | | in the multiword case. Rewrite getHiBits to use the class method version of lshr instead of the one in APIntOps. NFCI llvm-svn: 299243
* [DAGCombiner] remove redundant code and add comments; NFCISanjay Patel2017-03-311-10/+13
| | | | llvm-svn: 299241
* [AArch64] Add new subtarget feature to fold LSL into address mode.Balaram Makam2017-03-313-5/+53
| | | | | | | | | | | | | Summary: This feature enables folding of logical shift operations of up to 3 places into addressing mode on Kryo and Falkor that have a fastpath LSL. Reviewers: mcrosier, rengolin, t.p.northover Subscribers: junbuml, gberry, llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D31113 llvm-svn: 299240
* [AVX-512] Update lowering for gather/scatter prefetch intrinsics to match ↵Craig Topper2017-03-311-3/+3
| | | | | | | | | | the immediate encodings the frontend uses based on the _MM_HINT_T0/T1 constant values in clang's headers. Our _MM_HINT_T0/T1 constant values are 3/2 which matches gcc, but not icc or Intel documentation. Interestingly gcc had this same bug on their implementation of the gather/scatter builtins at one point too. Fixes PR32411. llvm-svn: 299234
* Fix the InstCombine to reserve the VP metadata and sets correct call count.Dehao Chen2017-03-312-8/+23
| | | | | | | | | | | | | | Summary: Currently the VP metadata was dropped when InstCombine converts a call to direct call. This patch converts the VP metadata to branch_weights so that its hotness is recorded. Reviewers: eraman, davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31344 llvm-svn: 299228
* Refactor code to create getFallThrough method in MachineBasicBlock.Jan Sjodin2017-03-311-8/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D27264 llvm-svn: 299227
* Remove name space pollution from Signals.cppKristof Beyls2017-03-313-5/+4
| | | | llvm-svn: 299224
* [mips][msa] Prevent output operand from commuting for dpadd_[su].df insPetar Jovanovic2017-03-312-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation of TargetInstrInfo::findCommutedOpIndices for MIPS target, restricting commutativity to second and third operand only for dpaadd_[su].df instructions therein. Prior to this change, there were cases where the vector that is to be added to the dot product of the other two could take a position other than the first one in the instruction, generating false output in the destination vector. Such behavior has been noticed in the two functions generating v2i64 output values so far. Other ones may exhibit such behavior as well, just not for the vector operands which are present in the test at the moment. Tests altered so that the function's first operand is a constant splat so that it can be loaded with a ldi instruction, since that is the case in which the erroneous instruction operand placement has occurred. We check that the register which is present in the ldi instruction is placed as the first operand in the corresponding dpadd instruction. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D30827 llvm-svn: 299223
* Remove more name space pollution from .inc filesKristof Beyls2017-03-314-20/+16
| | | | llvm-svn: 299222
* [DAGCombiner] Add ComputeNumSignBits vector demanded elements support to ↵Simon Pilgrim2017-03-311-1/+35
| | | | | | | | ASHR and INSERT_VECTOR_ELT Followup to D31311 llvm-svn: 299221
* [SystemZ] Make sure of correct regclasses in insertSelect()Jonas Paulsson2017-03-311-0/+6
| | | | | | | | | Since LOCR only accepts GR32 virtual registers, its operands must be copied into this regclass in insertSelect(), when an LOCR is built. Otherwise, the case where the source operand was GRX32 will produce invalid IR. Review: Ulrich Weigand llvm-svn: 299220
* [DAGCombiner] Add vector demanded elements support to ComputeNumSignBitsSimon Pilgrim2017-03-316-12/+43
| | | | | | | | | | | | | | Currently ComputeNumSignBits returns the minimum number of sign bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original ComputeNumSignBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. I've only added support for BUILD_VECTOR and EXTRACT_VECTOR_ELT so far, all others will default to demanding all elements but can be updated in due course. Followup to D25691. Differential Revision: https://reviews.llvm.org/D31311 llvm-svn: 299219
* Do not pollute the namespace in a header file.Kristof Beyls2017-03-311-1/+0
| | | | llvm-svn: 299218
* [SystemZ] Skip DAGCombining of vector node for older subtargets.Jonas Paulsson2017-03-311-0/+6
| | | | | | | | | | | | | Even on older subtargets that lack vector support, there may be vector values with just one element in the input program. These are converted during DAG legalization to scalar values. The pre-legalize SystemZ DAGCombiner methods should in this circumstance not touch these nodes. This patch adds a check for this in SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(). Review: Ulrich Weigand llvm-svn: 299213
* Make naming in Host.h in line with coding standards.Kristof Beyls2017-03-312-12/+12
| | | | | | | Based on post-commit review comments by Chandler Carruth on https://reviews.llvm.org/D31236. Thanks! llvm-svn: 299211
* Update comment for r299098 per feedback from James Henderson.Yaron Keren2017-03-311-2/+1
| | | | llvm-svn: 299207
* [ScalarEvolution] Re-enable Predicate implication from operationsMax Kazantsev2017-03-311-16/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch rL298481 was reverted due to crash on clang-with-lto-ubuntu build. The reason of the crash was type mismatch between either a or b and RHS in the following situation: LHS = sext(a +nsw b) > RHS. This is quite rare, but still possible situation. Normally we need to cast all {a, b, RHS} to their widest type. But we try to avoid creation of new SCEV that are not constants to avoid initiating recursive analysis that can take a lot of time and/or cache a bad value for iterations number. To deal with this, in this patch we reject this case and will not try to analyze it if the type of sum doesn't match with the type of RHS. In this situation we don't need to create any non-constant SCEVs. This patch also adds an assertion to the method IsProvedViaContext so that we could fail on it and not go further into range analysis etc (because in some situations these analyzes succeed even when the passed arguments have wrong types, what should not normally happen). The patch also contains a fix for a problem with too narrow scope of the analysis caused by wrong usage of predicates in recursive invocations. The regression test on the said failure: test/Analysis/ScalarEvolution/implied-via-addition.ll Reviewers: reames, apilipenko, anna, sanjoy Reviewed By: sanjoy Subscribers: mzolotukhin, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D31238 llvm-svn: 299205
* Do not pollute the namespace in a header file.Kristof Beyls2017-03-311-7/+7
| | | | llvm-svn: 299203
* [AMDGPU] SDWA Peephole: improve search for immediates in SDWA patternsSam Kolton2017-03-314-43/+75
| | | | | | | | | | | | | | | | | Previously compiler often extracted common immediates into specific register, e.g.: ``` %vreg0 = S_MOV_B32 0xff; %vreg2 = V_AND_B32_e32 %vreg0, %vreg1 %vreg4 = V_AND_B32_e32 %vreg0, %vreg3 ``` Because of this SDWA peephole failed to find SDWA convertible pattern. E.g. in previous example this could be converted into 2 SDWA src operands: ``` SDWA src: %vreg2 src_sel:BYTE_0 SDWA src: %vreg4 src_sel:BYTE_0 ``` With this change peephole check if operand is either immediate or register that is copy of immediate. llvm-svn: 299202
* [DAGCombiner] Add vector demanded elements support to ↵Simon Pilgrim2017-03-3116-6/+18
| | | | | | | | | | computeKnownBitsForTargetNode Follow up to D25691, this sets up the plumbing necessary to support vector demanded elements support in known bits calculations in target nodes. Differential Revision: https://reviews.llvm.org/D31249 llvm-svn: 299201
* Spelling mistakes in comments. NFCI.Simon Pilgrim2017-03-312-2/+2
| | | | llvm-svn: 299197
* Fix MSVC 'not all control paths return a value' warningSimon Pilgrim2017-03-311-0/+1
| | | | llvm-svn: 299195
* Fix signed/unsigned warningSimon Pilgrim2017-03-311-1/+1
| | | | llvm-svn: 299194
* [Scalarizer] Handle scalar arguments in vector GEPMikael Holmen2017-03-311-3/+16
| | | | | | | | | | | | | | | | | | Summary: Triggered by commit r298620: "[LV] Vectorize GEPs". If we encounter a vector GEP with scalar arguments, we splat the scalar into a vector of appropriate size before we scatter the argument. Reviewers: arsenm, mehdi_amini, bkramer Reviewed By: arsenm Subscribers: bjope, mssimpso, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D31416 llvm-svn: 299186
* Re-apply r299168 and r299169 now that the libdeps are fixed.Peter Collingbourne2017-03-313-127/+314
| | | | llvm-svn: 299184
* Move llvm::emitLinkerFlagsForGlobalCOFF() to Mangler.Peter Collingbourne2017-03-314-33/+33
| | | | llvm-svn: 299183
* Move llvm::canBeOmittedFromSymbolTable() to Analysis.Peter Collingbourne2017-03-313-20/+2
| | | | llvm-svn: 299182
* [libFuzzer] simplify the code a bitKostya Serebryany2017-03-313-17/+14
| | | | llvm-svn: 299180
* [libFuzzer] tests: don't test 64-bit comparison on 32-bit buildsKostya Serebryany2017-03-312-5/+7
| | | | llvm-svn: 299179
* [libFuzzer] ensure that strncmp is not inlined in a testKostya Serebryany2017-03-311-1/+2
| | | | llvm-svn: 299177
* Revert r299168 and r299169 due to library dependency issues.Peter Collingbourne2017-03-313-314/+127
| | | | | | http://bb.pgr.jp/builders/i686-mingw32-RA-on-linux/builds/25073/steps/build_llvmclang/logs/stdio llvm-svn: 299171
* LTO: Reduce memory consumption by creating an in-memory symbol table for ↵Peter Collingbourne2017-03-313-127/+314
| | | | | | | | | | | | | | | | | | | | | | | InputFiles. NFCI. Introduce symbol table data structures that can be potentially written to disk, have the LTO library build those data structures using temporarily constructed modules and redirect the LTO library implementation to go through those data structures. This allows us to remove the LLVMContext and Modules owned by InputFile. With this change I measured a peak memory consumption decrease from 5.4GB to 2.8GB in a no-op incremental ThinLTO link of Chromium on Linux. The impact on memory consumption is larger in COFF linkers where we are currently forced to materialize all metadata in order to read linker options. Peak memory consumption linking a large piece of Chromium for Windows with full LTO and debug info decreases from >64GB (OOM) to 15GB. Part of PR27551. Differential Revision: https://reviews.llvm.org/D31364 llvm-svn: 299168
* [libFuzzer] make sure we don't execute libFuzzer's mem* and str* hooks while ↵Kostya Serebryany2017-03-315-9/+17
| | | | | | calling mem*/str* inside libFuzzer itself llvm-svn: 299167
* Temporarily revert "[PPC] In PPCBoolRetToInt change the bool value to i64 if ↵Eric Christopher2017-03-313-37/+19
| | | | | | | | the target is ppc64" as it's causing test failures, I've given Carrot a testcase offline. This reverts commit r298955. llvm-svn: 299153
* Fix typo, defind -> defined.Eric Christopher2017-03-311-1/+1
| | | | llvm-svn: 299149
* [libFuzzer] try to fix value-profile-strncmp on the Mac botKostya Serebryany2017-03-311-1/+1
| | | | llvm-svn: 299145
* ModuleSummaryAnalysis: Use a more precise #include. NFC.Peter Collingbourne2017-03-311-1/+1
| | | | llvm-svn: 299142
* [WebAssembly] Initial linking metadata supportDan Gohman2017-03-307-36/+213
| | | | | | | | | | | | | | | | Add support for the new relocations and linking metadata section support in https://github.com/WebAssembly/tool-conventions/blob/master/Linking.md. In particular, this allows LLVM to indicate which variable is the stack pointer, so that it can be linked with other objects. This also adds support for emitting type relocations for call_indirect instructions. Right now, this is mainly tested by using wabt and hexdump to examine the output on selected testcases. We'll add more tests as the design stablizes and more of the pieces are in place. llvm-svn: 299141
* AMDGPU: Rename isKernelMatt Arsenault2017-03-303-6/+22
| | | | | | | | What we really want to do is distinguish functions that may be called by other functions, and graphics shaders are not called kernels. llvm-svn: 299140
* ThinLTOBitcodeWriter: Use Module::global_values(). NFCI.Peter Collingbourne2017-03-301-25/+7
| | | | llvm-svn: 299132
* getPristineRegs is not accurately considering shrink wrapping putsEric Christopher2017-03-303-2/+8
| | | | | | | | | | | registers not saved in certain blocks. Use explicit getCalleeSavedInfo and isLiveIn instead. This fixes pr32292. Patch by Tim Shen! llvm-svn: 299124
* [InstCombine] Fix typo last->least. NFCCraig Topper2017-03-301-3/+3
| | | | llvm-svn: 299123
* AMDGPU: Add all atomicrmw fields to atomic.inc/decMatt Arsenault2017-03-302-4/+13
| | | | | | Add scope, order, isVolatile llvm-svn: 299122
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