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author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2017-03-31 14:06:59 +0000 |
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committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2017-03-31 14:06:59 +0000 |
commit | c7bb22e75f8418ff867dc0b9702aab653da11f30 (patch) | |
tree | 7cbffe57d00790a01f57d439c508e761419f512a /llvm/lib | |
parent | 3c81c34d8d8a5f9e9abde0fcfedce91dc1d09156 (diff) | |
download | bcm5719-llvm-c7bb22e75f8418ff867dc0b9702aab653da11f30.tar.gz bcm5719-llvm-c7bb22e75f8418ff867dc0b9702aab653da11f30.zip |
[SystemZ] Make sure of correct regclasses in insertSelect()
Since LOCR only accepts GR32 virtual registers, its operands must be copied
into this regclass in insertSelect(), when an LOCR is built. Otherwise, the
case where the source operand was GRX32 will produce invalid IR.
Review: Ulrich Weigand
llvm-svn: 299220
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index f3eed05e88e..c8ff9558cc8 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -679,6 +679,12 @@ void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB, else { Opc = SystemZ::LOCR; MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass); + unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); + unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); + BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); + BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); + TrueReg = TReg; + FalseReg = FReg; } } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) Opc = SystemZ::LOCGR; |