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* AMDGPU: Legalize the operand of SI_INIT_M0Nicolai Haehnle2018-04-201-0/+15
| | | | | | | | | | | | | | | | | | | | Summary: This fixes a case where the argument to a sendmsg intrinsic ends up in a VGPR, for whatever reason. The underlying performance issue is that a multiplication that can be an s_mul_i32 is instead needlessly generated as v_mul_u32_u24, but this is not addressed by this patch. Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328 Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45826 llvm-svn: 330393
* [Sparc] Fix addressing mode when using 64-bit values in inline assemblyDaniel Cederman2018-04-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a 64-bit register is used as an operand in inline assembly together with a memory reference, the memory addressing will be wrong. The addressing will be a single reg, instead of reg+reg or reg+imm. This will generate a bad offset value or an exception in printMemOperand(). For example: ``` long long int val = 5; long long int mem; __asm__ volatile ("std %1, %0":"=m"(mem):"r"(val)); ``` becomes: ``` std %i0, [%i2+589833] ``` The problem is that SelectInlineAsmMemoryOperand() is never called for the memory references if one of the operands is a 64-bit register. By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc version of SelectInlineAsmMemoryOperand() gets called for each memory reference. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45761 llvm-svn: 330392
* LowerTypeTests: Propagate symver directivesVlad Tsyrklevich2018-04-205-38/+103
| | | | | | | | | | | | | | | | | | | | | | Summary: This change fixes https://crbug.com/834474, a build failure caused by LowerTypeTests not preserving .symver symbol versioning directives for exported functions. Emit symver information to ThinLTO summary data and then propagate symver directives for exported functions to the merged module. Emitting symver information to the summaries increases the size of intermediate build artifacts for a Chromium build by less than 0.2%. Reviewers: pcc Reviewed By: pcc Subscribers: tejohnson, mehdi_amini, eraman, llvm-commits, eugenis, kcc Differential Revision: https://reviews.llvm.org/D45798 llvm-svn: 330387
* Move a dump() implementation out of line.Amara Emerson2018-04-201-0/+11
| | | | | | Fixes some link issues. llvm-svn: 330384
* [MachineOutliner] NFC: Move EnableLinkOnceODROutlining into MachineOutliner.cppJessica Paquette2018-04-192-10/+20
| | | | | | | | | This moves the EnableLinkOnceODROutlining flag from TargetPassConfig.cpp into MachineOutliner.cpp. It also removes OutlineFromLinkOnceODRs from the MachineOutliner constructor. This is now handled by the moved command-line flag. llvm-svn: 330373
* [WebAssembly] Enabled -triple=wasm32-unknown-unknown-wasm path using ELF ↵Sam Clegg2018-04-191-3/+7
| | | | | | | | | | | | | | | | directive parser. This is a temporary solution until a proper WASM implementation of MCAsmParserExtension is in place, but at least for now will unblock this path. Added test to make sure this path works with the WASM Assembler. Patch By Wouter van Oortmerssen! Differential Revision: https://reviews.llvm.org/D45386 llvm-svn: 330370
* [AMDGPU] Use packed literals with zero either lower or hi partStanislav Mekhanoshin2018-04-192-2/+21
| | | | | | Differential Revision: https://reviews.llvm.org/D45790 llvm-svn: 330365
* Refine the loop rotation's APIJin Lin2018-04-192-12/+21
| | | | | | | | | | | | | | | | Summary: The following changes addresses the following two issues. 1) The existing loop rotation pass contains both loop latch simplification and loop rotation. So one flag RotationOnly is added to be passed to the loop rotation pass. 2) The threshold value is initialized with MAX_UINT since the loop rotation utility should not have threshold limit. Reviewers: dmgreen, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D45582 llvm-svn: 330362
* [ORC] Fix an assertion condition from r329934.Lang Hames2018-04-191-2/+2
| | | | | | Thanks to Alexander Ivchenko for finding the issue! llvm-svn: 330359
* [X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.Craig Topper2018-04-191-2/+6
| | | | | | Silvermont and Goldmont have the same issue on popcnt as Sandy Bridge, Haswell, Broadwell, and Skylake. Believe it is fixed in Goldmont Plus. llvm-svn: 330358
* [PM/LoopUnswitch] Detect irreducible control flow within loops and skip ↵Chandler Carruth2018-04-191-0/+13
| | | | | | | | | | | | | | | | | | | | unswitching non-trivial edges. Summary: This fixes the bug pointed out in review with non-trivial unswitching. This also provides a basis that should make it pretty easy to finish fleshing out a routine to scan an entire function body for irreducible control flow, but this patch remains minimal for disabling loop unswitch. Reviewers: sanjoy, fedor.sergeev Subscribers: mcrosier, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45754 llvm-svn: 330357
* [ORC] Make VSO symbol resolution/finalization operations private.Lang Hames2018-04-191-85/+109
| | | | | | | | This forces these operations to be carried out via a MaterializationResponsibility instance, ensuring responsibility is explicitly tracked. llvm-svn: 330356
* [X86][SLM] Fix typo using SandyBridge resources. Simon Pilgrim2018-04-191-2/+2
| | | | | | Luckily this was on instructions not supported on Silvermont.... llvm-svn: 330351
* [X86] Correct the scheduling data for register forms of XCHG and XADD on ↵Craig Topper2018-04-195-22/+24
| | | | | | | | | | | | Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
* [Reassociate] fix formatting; NFCSanjay Patel2018-04-191-4/+3
| | | | llvm-svn: 330348
* [X86] Merge some MMX instregexSimon Pilgrim2018-04-195-269/+88
| | | | | | There's a lot more but I'd prefer focussing on removing unnecessary InstRWs first. llvm-svn: 330347
* [if-converter] Handle BBs that terminate in ret during diamond conversionKrzysztof Parzyszek2018-04-191-11/+28
| | | | | | | | | | This fixes https://llvm.org/PR36825. Original patch by Valentin Churavy (D45218). Differential Revision: https://reviews.llvm.org/D45731 llvm-svn: 330345
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+26
| | | | llvm-svn: 330344
* [llvm-objdump] Print "..." instead of random data for virtual sectionsFrancis Visoiu Mistrih2018-04-191-2/+4
| | | | | | | | | | | | | | | | | When disassembling with -D, skip virtual sections by printing "..." for each symbol. This patch also implements `MachOObjectFile::isSectionVirtual`. Test case comes from: ``` .zerofill __DATA,__common,_data64unsigned,472,3 ``` Differential Revision: https://reviews.llvm.org/D45824 llvm-svn: 330342
* [AMDGPU] Do not only rely on BB number when finding bottom loopMark Searles2018-04-191-20/+45
| | | | | | | | We should also check that the "bottom" basic block of a loopis a successor of the "header" basic block, otherwise we don't propagate the information correctly when the CFG is complex. This fixes an important rendering problem with Wolfsentein 2, because of one vector-memory wait was missing. Differential Revision: https://reviews.llvm.org/D43831 llvm-svn: 330337
* [NewGVN] Add ops as dependency if we cannot find a leader for ValueOp.Florian Hahn2018-04-191-2/+11
| | | | | | | | | | | | | | | | | If those operands change, we might find a leader for ValueOp, which could enable new phi-of-op creation. This fixes a case where we missed creating a phi-of-ops node. With D43865 and this patch, bootstrapping clang/llvm works with -enable-newgvn, whereas without it, the "value changed after iteration" assertion is triggered. Reviewers: dberlin, davide Reviewed By: dberlin Differential Revision: https://reviews.llvm.org/D42180 llvm-svn: 330334
* [Hexagon] Generate code for vector bswap intrinsicsKrzysztof Parzyszek2018-04-191-0/+5
| | | | llvm-svn: 330333
* [X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.Simon Pilgrim2018-04-191-4/+0
| | | | | | These are already handled identically by WriteALU. llvm-svn: 330332
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-192-99/+89
| | | | llvm-svn: 330330
* [mips] Correct the definitions of the unaligned word memory operation ↵Simon Dardis2018-04-194-25/+40
| | | | | | | | | | | | | | | | instructions These instructions lacked the correct predicates, were not marked as loads and stores and lacked the proper instruction mapping information. In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load EVA description. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45626 llvm-svn: 330326
* Lowering x86 adds/addus/subs/subus intrinsics (llvm part)Alexander Ivchenko2018-04-193-42/+193
| | | | | | | | | | | | | This is the patch that lowers x86 intrinsics to native IR in order to enable optimizations. The patch also includes folding of previously missing saturation patterns so that IR emits the same machine instructions as the intrinsics. Patch by tkrupa Differential Revision: https://reviews.llvm.org/D44785 llvm-svn: 330322
* [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides.Simon Pilgrim2018-04-194-25/+1
| | | | | | These are all already handled identically by WriteFMA. llvm-svn: 330319
* [X86][BtVer2] Remove 128-bit F16C InstRW overrides.Simon Pilgrim2018-04-191-10/+0
| | | | | | These are already handled identically by WriteCvtF2F. llvm-svn: 330318
* [BasicBlock] Add instructionsWithoutDebug methods to skip debug insts.Florian Hahn2018-04-191-0/+18
| | | | | | | | | | Reviewers: aprantl, vsk, mattd, chandlerc Reviewed By: aprantl, vsk Differential Revision: https://reviews.llvm.org/D45657 llvm-svn: 330316
* [mips] Guard some macro expansions properlySimon Dardis2018-04-193-20/+24
| | | | | | | | Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D45565 llvm-svn: 330315
* [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers.Sander de Smalen2018-04-191-77/+69
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Renamed tryParseRegister to tryParseScalarRegister, which now returns an OperandMatchResultTy. - Moved matching of certain aliases into matchRegisterNameAlias. - Changed type of most 'Reg' variables to 'unsigned'. This is patch [1/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro, samparker Reviewed By: samparker Subscribers: samparker, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45687 llvm-svn: 330311
* [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs.Craig Topper2018-04-195-35/+81
| | | | | | This removes a bunch of unnecessary InstRW overrides. It also cleans up the missing information from the Sandy Bridge model. Other fixes to other models. llvm-svn: 330308
* Fix data race in X86FloatingPoint.cpp ASSERT_SORTEDBob Haarman2018-04-181-7/+8
| | | | | | | | | | | | | | | | | | | | | Summary: ASSERT_SORTED checks if a table is sorted, and uses a boolean to prevent the check from being run again if it was earlier determined that the table is in fact sorted. Unsynchronized reads and writes of that boolean triggered ThreadSanitizer's data race detection. This change rewrites the code to use std::atomic<bool> instead. Fixes PR36922. Reviewers: rnk Reviewed By: rnk Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D45742 llvm-svn: 330301
* [X86] Correct the Defs, Uses, hasSideEffects, mayLoad, mayStore for XCHG and ↵Craig Topper2018-04-183-35/+52
| | | | | | | | XADD instructions. I don't think we emit any of these from codegen except for using XCHG16ar as 2 byte NOP. llvm-svn: 330298
* [NVPTX, CUDA] Added support for m8n32k16 and m32n8k16 variants of wmma ↵Artem Belevich2018-04-184-17/+85
| | | | | | | | | | instructions. The new instructions were added added for sm_70+ GPUs in CUDA-9.1. Differential Revision: https://reviews.llvm.org/D45068 llvm-svn: 330296
* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-181-2/+3
| | | | | | | These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
* [X86] Fix the Uses/Defs,mayLoad,mayStore,hasSideEffects flags for the ↵Craig Topper2018-04-181-6/+13
| | | | | | | | CMPXCHG instructions. The compiler only emits the locked version of these which use different instruction definitions. The versions fixed here are only used by the assembler/disassembler. llvm-svn: 330287
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-189-266/+49
| | | | | | | | | Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
* [Power9]Legalize and emit code for converting Unsigned HWord/Char to ↵Lei Huang2018-04-181-0/+8
| | | | | | | | | | | | | | | | Quad-Precision Legalize and emit code for converting unsigned HWord/Char to QP: xscvsdqp xscvudqp Only covering patterns for unsigned forms cause we don't have part-word sign-extending integer loads into VSX registers. Differential Revision: https://reviews.llvm.org/D45494 llvm-svn: 330278
* [AArch64] Add isel pattern for v8i8->v2f32 NVCASTs.Amara Emerson2018-04-181-0/+1
| | | | | | rdar://39454635 llvm-svn: 330276
* [Power9]Legalize and emit code for converting (Un)Signed Word to Quad-PrecisionLei Huang2018-04-181-1/+10
| | | | | | | | | | | Legalize and emit code for converting (Un)Signed Word to quad-precision via: xscvsdqp xscvudqp Differential Revision: https://reviews.llvm.org/D45389 llvm-svn: 330273
* [DEBUG] Initial adaptation of NVPTX target for debug info emission.Alexey Bataev2018-04-1812-280/+222
| | | | | | | | | | | | | | | Summary: Patch adds initial emission of the debug info for NVPTX target. Currently, only .file and .loc directives are emitted, everything else is commented out to not break the compilation of Cuda. Reviewers: echristo, jlebar, tra, jholewinski Subscribers: mgorny, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41827 llvm-svn: 330271
* [x86] Switch EFLAGS copy lowering to use reg-reg form of testing forChandler Carruth2018-04-181-1/+1
| | | | | | | | | | | | | | | | a zero register. Previously I tried this and saw LLVM unable to transform this to fold with memory operands such as spill slot rematerialization. However, it clearly works as shown in this patch. We turn these into `cmpb $0, <mem>` when useful for folding a memory operand without issue. This form has no disadvantage compared to `testb $-1, <mem>`. So overall, this is likely no worse and may be slightly smaller in some cases due to the `testb %reg, %reg` form. Differential Revision: https://reviews.llvm.org/D45475 llvm-svn: 330269
* [support] Revert the changes made to Path.inc for the default Windows code pageAaron Smith2018-04-181-11/+5
| | | | | | | | | Path.inc/widenPath tries to decode the path using both UTF-8 and the default Windows code page. This is no longer necessary with the new InitLLVM method which ensures that the command line arguemnts are already UTF-8 on Windows. llvm-svn: 330266
* [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite usesChandler Carruth2018-04-181-82/+125
| | | | | | | | | | | | | | | | | | | | | | across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 llvm-svn: 330264
* [SimplifyLibcalls] Realloc(null, N) -> Malloc(N)Sanjay Patel2018-04-182-21/+46
| | | | | | | | Patch by Dávid Bolvanský! Differential Revision: https://reviews.llvm.org/D45413 llvm-svn: 330259
* [AMDGPU] Fix issues for backend divergence trackingDavid Stuttard2018-04-182-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A change to use divergence analysis in the AMDGPU backend was getting formal arguments incorrect (not tagged as divergent) unless they were VGPR0, VGPR1 or VGPR2 For graphics shaders it is possible to have more than these passed in as VGPR Modified the checking code to check for any VGPR registers passed in as formal arguments. Also, some intrinsics that are sources of divergence may have been lowered during instruction selection and are missed on subsequent calls to isSDNodeSourceOfDivergence - added the relevant AMDGPUISD checks as well. Finally, the FunctionLoweringInfo tracks virtual registers that are live across basic block boundaries. This is used to check for divergence of CopyFromRegister registers using the DivergenceAnalysis analysis. For multiple blocks the lazily evaluated inverted map VirtReg2Value was not cleared when the ValueMap map was. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45372 Change-Id: I112f3bd6dfe0f62e63ce9b43b893982778e4bee3 llvm-svn: 330257
* [IRCE] Only check for NSW on equality predicatesSam Parker2018-04-181-29/+14
| | | | | | | | | | | After investigation discussed in D45439, it would seem that the nsw flag restriction is unnecessary in most cases. So the IsInductionVar lambda has been removed, the functionality extracted, and now only require nsw when using eq/ne predicates. Differential Revision: https://reviews.llvm.org/D45617 llvm-svn: 330256
* [cmake] Improve pthread_[gs]etname_np detection codePavel Labath2018-04-181-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Due to some android peculiarities, in some build configurations (statically linked executables targeting older releases) we could detect the presence of these functions (because they are present in libc.a, where check_library_exists searches), but then fail to build because the headers did not include the definition. This attempts to remedy that by upgrading the check_library_exists to check_symbol_exists, which will check that the function is declared too. I am hoping that a more thorough check will make the messy #ifdef we have accumulated in the code obsolete, so I optimistically try to remove them. Reviewers: zturner, kparzysz, danalbert Subscribers: srhines, mgorny, krytarowski, llvm-commits Differential Revision: https://reviews.llvm.org/D45359 llvm-svn: 330251
* [LoopUnroll] Only peel if a predicate becomes known in the loop body.Florian Hahn2018-04-181-7/+25
| | | | | | | | | | | | | If a predicate does not become known after peeling, peeling is unlikely to be beneficial. Reviewers: mcrosier, efriedma, mkazantsev, junbuml Reviewed By: mkazantsev Differential Revision: https://reviews.llvm.org/D44983 llvm-svn: 330250
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