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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-19 14:38:36 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-19 14:38:36 +0000 |
| commit | f21ace6cdd6a406bfa80403f9386700d48b24d98 (patch) | |
| tree | e2ce22ec6327d210f1aac23dec9c31ae978e7a6b /llvm/lib | |
| parent | b127a394041c2defbf44e1c52cb34bee643f3e5b (diff) | |
| download | bcm5719-llvm-f21ace6cdd6a406bfa80403f9386700d48b24d98.tar.gz bcm5719-llvm-f21ace6cdd6a406bfa80403f9386700d48b24d98.zip | |
[X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.
These are already handled identically by WriteALU.
llvm-svn: 330332
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 2fc33354fa1..4f5784f4db8 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -488,10 +488,6 @@ def : InstRW<[JWriteDPPDLd], (instrs DPPDrmi, VDPPDrmi)>; // SSE4A instructions. //////////////////////////////////////////////////////////////////////////////// -def JWriteEXTRQ: SchedWriteRes<[JFPU01, JVALU]> { -} -def : InstRW<[JWriteEXTRQ], (instrs EXTRQ, EXTRQI)>; - def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> { let Latency = 2; let ResourceCycles = [1, 4]; |
