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* [X86] Use KMOV instructions to zero upper bits of vectors when possible.Craig Topper2017-12-091-12/+29
| | | | llvm-svn: 320268
* [X86] Improve lowering of vXi1 insert_subvectors to better utilize ↵Craig Topper2017-12-091-67/+87
| | | | | | | | (insert_subvector zero, vec, 0) for zeroing upper bits. This can be better recognized during isel when the producer already zeroed the upper bits. llvm-svn: 320267
* [X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classesSimon Pilgrim2017-12-091-3/+7
| | | | llvm-svn: 320266
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-092-13/+13
| | | | llvm-svn: 320265
* [X86] Tag FS/GS BASE R/W instruction scheduler classesSimon Pilgrim2017-12-092-9/+18
| | | | llvm-svn: 320264
* [X86] Tag REP/REPNE prefix instructions as microcoded scheduler classesSimon Pilgrim2017-12-091-3/+2
| | | | llvm-svn: 320263
* [X86] Tag missing EH pseudo instruction scheduler classesSimon Pilgrim2017-12-092-3/+4
| | | | llvm-svn: 320262
* [X86] Tag frame pointer XORs instruction scheduler classesSimon Pilgrim2017-12-091-2/+4
| | | | llvm-svn: 320261
* [X86] Don't use getTargetConstant for all 0s and all 1s mask vector.Craig Topper2017-12-091-10/+8
| | | | llvm-svn: 320260
* [X86] Tag segment prefixes as NOP instruction scheduling classesSimon Pilgrim2017-12-091-7/+8
| | | | llvm-svn: 320257
* [X86][AVX512] Drop a default NoItinerary argument that isn't used any more. ↵Simon Pilgrim2017-12-091-6/+6
| | | | | | | | NFCI. Requires re-ordering of AVX512_maskable_custom arguments. llvm-svn: 320255
* Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. ↵Simon Pilgrim2017-12-091-1/+1
| | | | | | NFCI. llvm-svn: 320254
* Fix signed/unsigned gcc warning. NFCI.Simon Pilgrim2017-12-091-1/+1
| | | | llvm-svn: 320253
* [InlineFunction] Set debug loc for call to forward varargs.Florian Hahn2017-12-091-0/+1
| | | | | | | | | | | | Reviewers: aprantl, dblaikie, rnk Reviewed By: rnk Subscribers: eraman, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D40432 llvm-svn: 320252
* [X86] When inserting into the upper bits of a vXi1 vector, make sure we ↵Craig Topper2017-12-091-1/+2
| | | | | | | | | | shift enough bits if we widened the vector. We may need to widen the vector to make the shifts legal, but if we do that we need to make sure we shift left/right after accounting for the new size. If not we can't guarantee we are shifting in zeros. The test cases affected actually show cases where we should move the shifts all together, but that's another problem. llvm-svn: 320248
* Revert and accidentally committed revert commitDylan McKay2017-12-0912-22/+285
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-0912-285/+22
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* [X86] Improve lowering of concats of mask vectors to better optimize zero ↵Craig Topper2017-12-091-59/+44
| | | | | | | | vector inputs. We were previously using kunpck with zero inputs unnecessarily. And we had cases where we would insert into a zero vector and then insert into larger zero vector incurring two sets of shifts. llvm-svn: 320244
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-093-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This relaxes an assertion inside SelectionDAGBuilder which is overly restrictive on targets which have no concept of alignment (such as AVR). In these architectures, all types are aligned to 8-bits. After this, LLVM will only assert that accesses are aligned on targets which actually require alignment. This patch follows from a discussion on llvm-dev a few months ago http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html Reviewers: bogner, nemanjai, joerg, efriedma Reviewed By: efriedma Subscribers: efriedma, cactus, llvm-commits Differential Revision: https://reviews.llvm.org/D39946 llvm-svn: 320243
* [MachineOutliner] Outline callsJessica Paquette2017-12-091-4/+118
| | | | | | | | | | | | | The outliner previously would never outline calls. Calls are pretty common in files, so it makes sense to outline them. In fact, in the LLVM test suite, if you count the number of instructions that the outliner misses when you outline calls vs when you don't, it turns out that, on average, around 6% of the instructions encountered are calls. So, if we outline calls, we can find more candidates, and thus save some more space. This commit adds that functionality and updates the mir test to reflect that. llvm-svn: 320229
* Register NetBSD/x86_64 in MemorySanitizer.cppKamil Rytarowski2017-12-091-0/+22
| | | | | | | | | | | | | | | | | | | Summary: Reuse the Linux new mapping as it is. Sponsored by <The NetBSD Foundation> Reviewers: joerg, eugenis, vitalybuka Reviewed By: vitalybuka Subscribers: llvm-commits, #sanitizers Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D41022 llvm-svn: 320219
* Hardware-assisted AddressSanitizer (llvm part).Evgeniy Stepanov2017-12-0916-15/+322
| | | | | | | | | | | | | | | | | | | | | Summary: This is LLVM instrumentation for the new HWASan tool. It is basically a stripped down copy of ASan at this point, w/o stack or global support. Instrumenation adds a global constructor + runtime callbacks for every load and store. HWASan comes with its own IR attribute. A brief design document can be found in clang/docs/HardwareAssistedAddressSanitizerDesign.rst (submitted earlier). Reviewers: kcc, pcc, alekseyshl Subscribers: srhines, mehdi_amini, mgorny, javed.absar, eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D40932 llvm-svn: 320217
* Fix out-of-order stepping behavior in programs with sunk instructions.Paul Robinson2017-12-091-1/+11
| | | | | | | | | | | | | | | | | | | MachineSink attempts to place instructions near the basic blocks where they are needed. Once an instruction has been sunk, its location relative to other instructions no longer is consistent with the original source code. In order to ensure correct stepping in the debugger, the debug location for sunk instructions is either merged with the insertion point or erased if the target successor block is empty. Originally submitted as r318679, revised to fix sanitizer failure and improve testing. Patch by Matthew Voss! Differential Revision: https://reviews.llvm.org/D39933 llvm-svn: 320216
* dwarfdump: Add support for the --diff option.Adrian Prantl2017-12-082-21/+29
| | | | | | | | | --diff Emit the output in a diff-friendly way by omitting offsets and addresses. <rdar://problem/34502625> llvm-svn: 320214
* [X86][Mips] Remove unused method declaration from the X86 and Mips AsmPrinters.Craig Topper2017-12-082-7/+0
| | | | | | Both had a declaration of EmitXRayTable, but there is no method defined in either with that name. There is a emitXRayTable in the base class with a lower case 'e' and they both call that. llvm-svn: 320213
* [CodeGen] Move printing MO_Immediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-083-9/+21
| | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Add support for operand subreg index as an immediate to debug printing and use ::print in the MIRPrinter. Differential Review: https://reviews.llvm.org/D40965 llvm-svn: 320209
* [AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp ↵Abderrazek Zaafrani2017-12-082-1/+1
| | | | | | | | to reflect the recently added features. The name change is dicsussed in https://reviews.llvm.org/D38196 llvm-svn: 320204
* Generalize llvm::replaceDbgDeclare and actually support the use-case thatAdrian Prantl2017-12-087-12/+25
| | | | | | is mentioned in the documentation (inserting a deref before the plus_uconst). llvm-svn: 320203
* [CodeExtractor] Add debug locations for new call and branch instrs.Florian Hahn2017-12-081-1/+24
| | | | | | | | | | | | | | | | | | | | | | | Summary: If a partially inlined function has debug info, we have to add debug locations to the call instruction calling the outlined function. We use the debug location of the first instruction in the outlined function, as the introduced call transfers control to this statement and there is no other equivalent line in the source code. We also use the same debug location for the branch instruction added to jump from artificial entry block for the outlined function, which just jumps to the first actual basic block of the outlined function. Reviewers: davide, aprantl, rriddle, dblaikie, danielcdh, wmi Reviewed By: aprantl, rriddle, danielcdh Subscribers: eraman, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D40413 llvm-svn: 320199
* [WebAssembly] Reapply r319186: "Support bitcasted function addresses with ↵Dan Gohman2017-12-081-1/+1
| | | | | | | | | varargs." This puts the functionality under control of a command-line option which is off by default to avoid breaking existing setups. llvm-svn: 320197
* [WebAssemby] Re-apply r320041: "Support main functions with alternate ↵Dan Gohman2017-12-081-1/+50
| | | | | | | | | | signatures." This includes a fix so that it doesn't transform declarations, and it puts the functionality under control of a command-line option which is off by default to avoid breaking existing setups. llvm-svn: 320196
* [AArch64] Add Exynos to host detectionEvandro Menezes2017-12-081-0/+31
| | | | | | Differential revision: https://reviews.llvm.org/D40985 llvm-svn: 320195
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-084-46/+21
| | | | | | | | | | | | - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
* [X86] CMOV pseudo instructions shouldn't need scheduling info as they should ↵Simon Pilgrim2017-12-081-2/+2
| | | | | | be lowered early llvm-svn: 320193
* [X86][X87] Tag x87 load/store instructions scheduler classesSimon Pilgrim2017-12-081-5/+11
| | | | llvm-svn: 320192
* [X86] Teach lowering to only let through (insert_subvector (vXi1 zeros), ↵Craig Topper2017-12-082-35/+18
| | | | | | | | | | | | subvec, 0) for vector sizes that have native KSHIFT support. For narrow sizes we'll widen the zero vector and widen the insert. Then do an extract_subvector to get back down to correct size. This allows us to remove some patterns from the isel table that had to COPY_TO_REGCLASS to an oversized register, do the shift and then COPY_TO_REGCLASS back to the narrow register. Now this is represented explicitly in the DAG. This seems to have perturbed the register allocation in one of the tests, but the number of instructions didn't change. llvm-svn: 320190
* [X86][X87] Tag x87 float compare instructions scheduler classesSimon Pilgrim2017-12-081-11/+15
| | | | llvm-svn: 320189
* AMDGPU: Set IntrReadMem on memtime intrinsicsMatt Arsenault2017-12-081-5/+2
| | | | llvm-svn: 320188
* AMDGPU: image_getlod and image_getresinfo do not read memoryMatt Arsenault2017-12-082-13/+40
| | | | llvm-svn: 320187
* AMDGPU: Preserve MMO in adjustWritemaskMatt Arsenault2017-12-081-0/+2
| | | | | | | | Follow up to r319705. Currently the MMO is produced after this in the custom inserter, so this doesn't change anything yet. llvm-svn: 320186
* Revert r320104: infinite loop profiling bug fixXinliang David Li2017-12-083-36/+38
| | | | | | | | | | | Causes unexpected memory issue with New PM this time. The new PM invalidates BPI but not BFI, leaving the reference to BPI from BFI invalid. Abandon this patch. There is a more general solution which also handles runtime infinite loop (but not statically). llvm-svn: 320180
* [JumpThreading] Minor comment cleanup. NFC. (test commit)Brian M. Rzycki2017-12-081-2/+2
| | | | llvm-svn: 320179
* [X86][MPX] Tag TSX/HLE/SGX instructions scheduler classesSimon Pilgrim2017-12-082-0/+7
| | | | | | Currently tagged these as system instructions. llvm-svn: 320177
* AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is ↵Konstantin Zhuravlyov2017-12-081-0/+2
| | | | | | | | not available Differential Revision: https://reviews.llvm.org/D40924 llvm-svn: 320176
* Reverting r320166 to fix test failures.Michael Trent2017-12-081-23/+1
| | | | llvm-svn: 320174
* [X86][MPX] Tag MPX instructions scheduler classesSimon Pilgrim2017-12-082-14/+19
| | | | | | Currently tagged these as system instructions, once we have uses for them (ASAN?) and they are faster we will need to improve on this. llvm-svn: 320173
* [x86] use hasAVX2() rather than hasInt256(); NFCSanjay Patel2017-12-081-3/+3
| | | | | | | | These are aliases, but the thing we're checking here is that the target has vpsllv*, not that the data type is 256-bit. Those instructions exist for 128-bit vectors too...but sadly, not for all element sizes. llvm-svn: 320170
* [X86] Tag move immediate instructions scheduler classesSimon Pilgrim2017-12-082-20/+29
| | | | llvm-svn: 320169
* Updated llvm-objdump to display local relocations in Mach-O binariesMichael Trent2017-12-081-1/+23
| | | | | | | | | | | | | | | | | | | | Summary: llvm-objdump's Mach-O parser was updated in r306037 to display external relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O parser to display local relocations for MH_PRELOAD files. When used with the -macho option relocations will be displayed in a historical format. rdar://35778019 Reviewers: enderby Reviewed By: enderby Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40867 llvm-svn: 320166
* [X86][SHA] Tag SHA instructions scheduler classesSimon Pilgrim2017-12-081-11/+22
| | | | | | Put these under VecIMul itinerary classes for now - seems to be a good average value llvm-svn: 320161
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