[X86] Teach lowering to only let through (insert_subvector (vXi1 zeros), subvec, 0) for vector sizes that have native KSHIFT support.

For narrow sizes we'll widen the zero vector and widen the insert. Then do an extract_subvector to get back down to correct size.

This allows us to remove some patterns from the isel table that had to COPY_TO_REGCLASS to an oversized register, do the shift and then COPY_TO_REGCLASS back to the narrow register. Now this is represented explicitly in the DAG.

This seems to have perturbed the register allocation in one of the tests, but the number of instructions didn't change.

llvm-svn: 320190

2 files changed, 18 insertions, 35 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f31398c10a3..5bde801bbf7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -5017,14 +5017,25 @@ static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
   if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
     return Op;
 
+  MVT OpVT = Op.getSimpleValueType();
+  unsigned NumElems = OpVT.getVectorNumElements();
+
   // Inserting into the lsbs of a zero vector is legal. ISel will insert shifts
   // if necessary.
-  if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode()))
+  if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) {
+    if ((!Subtarget.hasDQI() && NumElems == 8) || (NumElems < 8)) {
+      // Need to promote to v16i1, do the insert, then extract back.
+      Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1, 
+                       getZeroVector(MVT::v16i1, Subtarget, DAG, dl),
+                       SubVec, Idx);
+      return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op,
+                         DAG.getIntPtrConstant(0, dl));
+    }
+
     return Op;
+  }
 
-  MVT OpVT = Op.getSimpleValueType();
   MVT SubVecVT = SubVec.getSimpleValueType();
-  unsigned NumElems = OpVT.getVectorNumElements();
   unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
 
   assert(IdxVal + SubVecNumElems <= NumElems &&
diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td b/llvm/lib/Target/X86/X86InstrVecCompiler.td
index 522744c06ec..900ce6eb7cf 100644
--- a/llvm/lib/Target/X86/X86InstrVecCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td
@@ -460,16 +460,16 @@ let Predicates = [HasAVX512] in {
             (COPY_TO_REGCLASS VK8:$src, VK16)>;
 }
 
-let Predicates = [HasVLX] in {
-  def : Pat<(v4i1 (insert_subvector (v4i1 immAllZerosV),
-                                    maskzeroupperv2i1:$src, (iPTR 0))),
-            (COPY_TO_REGCLASS VK2:$src, VK4)>;
+let Predicates = [HasVLX, HasDQI] in {
   def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
                                     maskzeroupperv2i1:$src, (iPTR 0))),
             (COPY_TO_REGCLASS VK2:$src, VK8)>;
   def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
                                     maskzeroupperv4i1:$src, (iPTR 0))),
             (COPY_TO_REGCLASS VK4:$src, VK8)>;
+}
+
+let Predicates = [HasVLX] in {
   def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
                                      maskzeroupperv2i1:$src, (iPTR 0))),
             (COPY_TO_REGCLASS VK2:$src, VK16)>;
@@ -502,35 +502,7 @@ let Predicates = [HasAVX512] in {
                                     (i8 8)), (i8 8))>;
 }
 
-let Predicates = [HasVLX, NoDQI] in {
-  // TODO can we legalize this out
-  def : Pat<(v4i1 (insert_subvector (v4i1 immAllZerosV),
-                                    (v2i1 VK2:$mask), (iPTR 0))),
-            (COPY_TO_REGCLASS (KSHIFTRWri
-                               (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16),
-                                           (i8 14)), (i8 14)), VK4)>;
-
-  // TODO can we legalize these out without dqi?
-  def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
-                                    (v2i1 VK2:$mask), (iPTR 0))),
-            (COPY_TO_REGCLASS (KSHIFTRWri
-                               (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16),
-                                           (i8 14)), (i8 14)), VK8)>;
-  def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
-                                    (v4i1 VK4:$mask), (iPTR 0))),
-            (COPY_TO_REGCLASS (KSHIFTRWri
-                               (KSHIFTLWri (COPY_TO_REGCLASS VK4:$mask, VK16),
-                                           (i8 12)), (i8 12)), VK8)>;
-}
-
 let Predicates = [HasVLX, HasDQI] in {
-  // TODO can we legalize this out
-  def : Pat<(v4i1 (insert_subvector (v4i1 immAllZerosV),
-                                    (v2i1 VK2:$mask), (iPTR 0))),
-            (COPY_TO_REGCLASS (KSHIFTRBri
-                               (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8),
-                                           (i8 14)), (i8 14)), VK4)>;
-
   def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
                                     (v2i1 VK2:$mask), (iPTR 0))),
             (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8),