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* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-011-1/+1
| | | | llvm-svn: 187581
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-012-0/+16
| | | | llvm-svn: 187580
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-012-54/+278
| | | | llvm-svn: 187576
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-016-58/+277
| | | | | | | | | | This also fixes a bug in the predication of LR to LOCR: I'd forgotten that with these in-place instruction builds, the implicit operands need to be added manually. I think this was latent until now, but is tested by int-cmp-45.c. It also adds a CC valid mask to STOC, again tested by int-cmp-45.c. llvm-svn: 187573
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-011-1/+25
| | | | | | | Convert >= 1 to > 0, etc. Using comparison with zero isn't a win on its own, but it exposes more opportunities for CC reuse (the next patch). llvm-svn: 187571
* Moving definition of MnemonicContainsDot field from class Instruction to ↵Vladimir Medic2013-08-012-1/+1
| | | | | | class AsmParser as suggested. llvm-svn: 187569
* AArch64: add initial NEON supportTim Northover2013-08-0117-35/+2649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
* XCore target: Fix Vararg handlingRobert Lytton2013-08-011-12/+14
| | | | llvm-svn: 187565
* XCore target: Add byval handlingRobert Lytton2013-08-011-11/+63
| | | | llvm-svn: 187563
* Xcore targetRobert Lytton2013-08-011-6/+9
| | | | | | Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line llvm-svn: 187562
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-2/+7
| | | | | | | | 1) They should never be inlined. 2) A naming inconsistency with gcc mips16 3) Stubs should not have the global attribute llvm-svn: 187555
* Add an omitted IsCall=1.Reed Kotler2013-08-011-0/+1
| | | | llvm-svn: 187553
* Option parsing: add support for alias arguments.Hans Wennborg2013-07-311-2/+20
| | | | | | | | | | | | | | | | | | This makes option aliases more powerful by enabling them to pass along arguments to the option they're aliasing. For example, if we have a joined option "-foo=", we can now specify a flag option "-bar" to be an alias of that, with the argument "baz". This is especially useful for the cl.exe compatible clang driver, where many options are aliases. For example, this patch enables us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to "-Werror" (again, -W is a joined option). Differential Revision: http://llvm-reviews.chandlerc.com/D1245 llvm-svn: 187537
* 80-colNadav Rotem2013-07-311-9/+14
| | | | llvm-svn: 187535
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-312-0/+30
| | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 llvm-svn: 187530
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-314-60/+19
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. llvm-svn: 187526
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-314-19/+23
| | | | | | This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051. llvm-svn: 187524
* R600: Do not mergevector after a vector reg is usedVincent Lejeune2013-07-311-1/+10
| | | | | | | | | | If we merge vector when a vector is used, it will generate an artificial antidependency that can prevent 2 tex/vtx instructions to use the same clause and thus generate extra clauses that reduce performance. There is no test case as such situation is really hard to predict. llvm-svn: 187516
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+5
| | | | llvm-svn: 187515
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-314-19/+60
| | | | llvm-svn: 187514
* R600: Don't mix LDS and non-LDS instructions in the same groupVincent Lejeune2013-07-311-0/+4
| | | | | | | | There are a lot of restrictions on instruction groups that contain LDS instructions, so for now we will be conservative and not packetize anything else with them. llvm-svn: 187513
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-07-314-23/+19
| | | | llvm-svn: 187512
* R600: Remove predicated_break instVincent Lejeune2013-07-314-59/+7
| | | | | | | | | | | | | We were using two instructions for similar purpose : break and predicated break. Only predicated_break was emitted and it was lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP. This commit simplify the situation by making AMDILCFGStructurizer emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which is now removed). There is no functionality change. llvm-svn: 187510
* Reject bitcasts between address spaces with different sizesMatt Arsenault2013-07-311-20/+104
| | | | llvm-svn: 187506
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-312-3/+21
| | | | | | | | | | The loop optimizers were assuming that scales > 1 were OK. I think this is actually a bug in TargetLoweringBase::isLegalAddressingMode(), since it seems to be trying to reject anything that isn't r+i or r+r, but it has no default case for scales other than 0, 1 or 2. Implementing the hook for z means that z can no longer test any change there though. llvm-svn: 187497
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-315-31/+31
| | | | | | | | Extend r187495 to conditional loads. I split this out because the easiest way seemed to be to force a particular operand order in SystemZISelDAGToDAG.cpp. llvm-svn: 187496
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-319-81/+137
| | | | | | | | | | | | | | | | | | | | | | | | System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. llvm-svn: 187495
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-314-136/+119
| | | | | | | | | | | | | | | | | | | | | | | r187116 moved compare-and-branch generation from the instruction-selection pass to the peephole optimizer (via optimizeCompare). It turns out that even this is a bit too early. Fused compare-and-branch instructions don't interact well with predication, where a CC result is needed. They also make it harder to reuse the CC side-effects of earlier instructions (not yet implemented, but the subject of a later patch). Another problem was that the AnalyzeBranch family of routines weren't handling compares and branches, so we weren't able to reverse the fused form in cases where we would reverse a separate branch. This could have been fixed by extending AnalyzeBranch, but given the other problems, I've instead moved the fusing to the long-branch pass, which is also responsible for the opposite transformation: splitting out-of-range compares and branches into separate compares and long branches. I've added a test for the AnalyzeBranch problem. A test for the predication problem is included in the next patch, which fixes a bug in the choice of CC mask. llvm-svn: 187494
* Fixed assertion in Extract128BitVector()Elena Demikhovsky2013-07-311-1/+2
| | | | llvm-svn: 187493
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-314-79/+193
| | | | | | | | | | | | | | | | | | | | | | r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. llvm-svn: 187492
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-316-181/+811
| | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. llvm-svn: 187491
* [SystemZ] Add RISBLG and RISBHG instruction definitionsRichard Sandiford2013-07-314-3/+19
| | | | | | The next patch will make use of RISBLG for codegen. llvm-svn: 187490
* Add parentheses to silence gcc warning.Richard Trieu2013-07-311-4/+4
| | | | llvm-svn: 187482
* Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.Craig Topper2013-07-311-1/+1
| | | | llvm-svn: 187477
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-319-230/+225
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* Fix a severe compile time problem when forming large SCEV expressions.Andrew Trick2013-07-311-0/+3
| | | | | | | | | | | | This fix is very lightweight. The same fix already existed for AddRec but was missing for NAry expressions. This is obviously an improvement and I'm unsure how to test compile time problems. Patch by Xiaoyi Guo! llvm-svn: 187475
* Remove trailing whitespace and some tab characters.Craig Topper2013-07-311-9/+9
| | | | llvm-svn: 187472
* Fixed incorrect disassembly for MOV16o16a when using Intel syntax.Craig Topper2013-07-311-2/+2
| | | | | | Patch by Richard Mitton. llvm-svn: 187471
* Fix crashing on invalid inline asm with matching constraints.Eric Christopher2013-07-311-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For a testcase like the following: typedef unsigned long uint64_t; typedef struct { uint64_t lo; uint64_t hi; } blob128_t; void add_128_to_128(const blob128_t *in, blob128_t *res) { asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in)); } where we'll fail to allocate the register for the output constraint, our matching input constraint will not find a register to match, and could try to search past the end of the current operands array. On the idea that we'd like to attempt to keep compilation going to find more errors in the module, change the error cases when we're visiting inline asm IR to return immediately and avoid trying to create a node in the DAG. This leaves us with only a single error message per inline asm instruction, but allows us to safely keep going in the general case. llvm-svn: 187470
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-311-4/+4
| | | | | | No functionality change. llvm-svn: 187469
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-315-38/+49
| | | | | | No functionality change. llvm-svn: 187468
* Fix ptr vector inconsistency in CreatePointerCastMatt Arsenault2013-07-311-5/+13
| | | | | | | | One form would accept a vector of pointers, and the other did not. Make both accept vectors of pointers, and add an assertion for the number of elements. llvm-svn: 187464
* Fix windows' implementation of status when a file doesn't exist.Rafael Espindola2013-07-311-6/+11
| | | | | | | | | The unix one was returning no_such_file_or_directory, but the windows one was return success. Update the one one caller that was depending on the old behavior. llvm-svn: 187463
* Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).Owen Anderson2013-07-301-4/+11
| | | | llvm-svn: 187462
* Reflow this to be easier to read.Eric Christopher2013-07-301-7/+5
| | | | llvm-svn: 187459
* Respect address space sizes in isEliminableCastPair.Matt Arsenault2013-07-302-14/+52
| | | | | | | This avoids constant folding bitcast/ptrtoint/inttoptr combinations that have illegal bitcasts between differently sized address spaces. llvm-svn: 187455
* Revert "Remove isCastable since nothing uses it now"Matt Arsenault2013-07-301-0/+63
| | | | | | Apparently dragonegg uses it. llvm-svn: 187454
* Remove isCastable since nothing uses it nowMatt Arsenault2013-07-301-63/+0
| | | | llvm-svn: 187448
* isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add ↵David Majnemer2013-07-301-16/+30
| | | | | | | | | instructions Call into ComputeMaskedBits to figure out which bits are set on both add operands and determine if the value is a power-of-two-or-zero or not. llvm-svn: 187445
* Change behavior of calling bitcasted alias functions.Matt Arsenault2013-07-302-11/+53
| | | | | | | | It will now only convert the arguments / return value and call the underlying function if the types are able to be bitcasted. This avoids using fp<->int conversions that would occur before. llvm-svn: 187444
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