[SystemZ] Add RISBLG and RISBHG instruction definitions

The next patch will make use of RISBLG for codegen.

llvm-svn: 187490

4 files changed, 19 insertions, 3 deletions

diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 5906ae5d9c9..6386d16b3d4 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -867,6 +867,13 @@ let Defs = [CC] in {
   def RISBG : RotateSelectRIEf<"risbg",  0xEC55, GR64, GR64>;
 }
 
+// Forms of RISBG that only affect one word of the destination register.
+// They do not set CC.
+def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
+             Requires<[FeatureHighWord]>;
+def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
+             Requires<[FeatureHighWord]>;
+
 // Rotate second operand left and perform a logical operation with selected
 // bits of the first operand.
 let Defs = [CC] in {
diff --git a/llvm/lib/Target/SystemZ/SystemZProcessors.td b/llvm/lib/Target/SystemZ/SystemZProcessors.td
index 96fa6a42d04..7e14aa75862 100644
--- a/llvm/lib/Target/SystemZ/SystemZProcessors.td
+++ b/llvm/lib/Target/SystemZ/SystemZProcessors.td
@@ -26,8 +26,13 @@ def FeatureLoadStoreOnCond : SystemZFeature<
   "Assume that the load/store-on-condition facility is installed"
 >;
 
+def FeatureHighWord : SystemZFeature<
+  "high-word", "HighWord",
+  "Assume that the high-word facility is installed"
+>;
+
 def : Processor<"z10",   NoItineraries, []>;
 def : Processor<"z196",  NoItineraries,
-                [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
+                [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;
 def : Processor<"zEC12", NoItineraries,
-                [FeatureDistinctOps, FeatureLoadStoreOnCond]>;
+                [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;
diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
index 43ac1ea4a69..036ec05d93a 100644
--- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -21,7 +21,7 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
                                    const std::string &CPU,
                                    const std::string &FS)
   : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
-    HasLoadStoreOnCond(false), TargetTriple(TT) {
+    HasLoadStoreOnCond(false), HasHighWord(false), TargetTriple(TT) {
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = "z10";
diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h
index 9d5dfc8a1de..4efb58d097b 100644
--- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h
+++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h
@@ -29,6 +29,7 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
 protected:
   bool HasDistinctOps;
   bool HasLoadStoreOnCond;
+  bool HasHighWord;
 
 private:
   Triple TargetTriple;
@@ -46,6 +47,9 @@ public:
   // Return true if the target has the load/store-on-condition facility.
   bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
 
+  // Return true if the target has the high-word facility.
+  bool hasHighWord() const { return HasHighWord; }
+
   // Return true if GV can be accessed using LARL for reloc model RM
   // and code model CM.
   bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,