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* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
| | | | llvm-svn: 129160
* Do not emit DW_AT_upper_bound and DW_AT_lower_bound for unbouded array.Devang Patel2011-04-081-3/+15
| | | | | | | | If lower bound is more then upper bound then consider it is an unbounded array. An array is unbounded if non-zero lower bound is same as upper bound. If lower bound and upper bound are zero than array has one element. llvm-svn: 129156
* Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng2011-04-083-25/+27
| | | | | | is lowered into a call to the specified trap function at sdisel time. llvm-svn: 129152
* Workaround g++ 4.2.1 warning diagnostic false positive.Jim Grosbach2011-04-081-2/+2
| | | | llvm-svn: 129149
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
| | | | llvm-svn: 129148
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
| | | | | | | PR9650 rdar://problem/9257565 llvm-svn: 129147
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-082-8/+29
| | | | | | | PR9648 rdar://problem/9257634 llvm-svn: 129146
* Mark hasExtraDefRegAllocReq=1 on LDRD.Jim Grosbach2011-04-081-1/+5
| | | | | | | | | The previous cleanup of LDRD got overzealous and removed it, causing post-RA scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued. rdar://9244161 llvm-svn: 129144
* Refactor MCJIT 32-bit section loading.Jim Grosbach2011-04-082-82/+67
| | | | | | | Teach 32-bit section loading to use the Memory Manager interface, just like the 64-bit loading does. Tidy up a few other things here and there. llvm-svn: 129138
* llvm.global_[cd]tor is defined to be either external, or appending with an arrayNick Lewycky2011-04-084-37/+33
| | | | | | | of { i32, void ()* }. Teach the verifier to verify that, deleting copies of checks strewn about. llvm-svn: 129128
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
| | | | | | Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
* Micro optimization and improved similarity with gas' output:Rafael Espindola2011-04-071-10/+38
| | | | | | When two section names share a suffix, reuse the entry in shstrtab. llvm-svn: 129115
* Do not let debug info interfer with branch folding.Devang Patel2011-04-071-0/+6
| | | | llvm-svn: 129114
* Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling2011-04-074-5/+22
| | | | | | | | | | | | | with the newer, cleaner model. It uses the IAPrinter class to hold the information that is needed to match an instruction with its alias. This also takes into account the available features of the platform. There is one bit of ugliness. The way the logic determines if a pattern is unique is O(N**2), which is gross. But in reality, the number of items it's checking against isn't large. So while it's N**2, it shouldn't be a massive time sink. llvm-svn: 129110
* Add option to emit @llvm.trap as a function call instead of a trap ↵Evan Cheng2011-04-071-1/+23
| | | | | | instruction. rdar://9249183. llvm-svn: 129107
* Add support for .skip.Rafael Espindola2011-04-071-1/+1
| | | | | | | Patch by Roman Divacky. Fixes PR9361. llvm-svn: 129106
* Fix indentation.Akira Hatanaka2011-04-071-2/+2
| | | | llvm-svn: 129105
* Update ATUsed every time after expandRegLargeImmPair is called.Akira Hatanaka2011-04-071-4/+8
| | | | llvm-svn: 129104
* Fixed encoding for VEXTqfMon P Wang2011-04-071-2/+2
| | | | llvm-svn: 129101
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-073-4/+107
| | | | | | | | | induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing llvm-svn: 129100
* Fix handling of functions with internal linkage.Akira Hatanaka2011-04-071-8/+27
| | | | llvm-svn: 129099
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-071-0/+5
| | | | | | | | extend instructions. Add some test cases. llvm-svn: 129098
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+5
| | | | llvm-svn: 129096
* Recompute hasPHIKill flags when shrinking live intervals.Jakob Stoklund Olesen2011-04-071-1/+3
| | | | | | PHI values may be deleted, causing the flags to be wrong. This fixes PR9616. llvm-svn: 129092
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+5
| | | | | | And two test cases. llvm-svn: 129090
* Expose more passes to the C API.Rafael Espindola2011-04-071-0/+16
| | | | llvm-svn: 129087
* Avoid moving iterators when the previous block was just visited.Jakob Stoklund Olesen2011-04-071-8/+13
| | | | llvm-svn: 129081
* Prefer multiplications to divisions.Jakob Stoklund Olesen2011-04-071-7/+13
| | | | llvm-svn: 129080
* Extract SpillPlacement::addLinks for handling the special transparent blocks.Jakob Stoklund Olesen2011-04-073-37/+49
| | | | llvm-svn: 129079
* While hoisting common code from if/else, hoist debug info intrinsics if they ↵Devang Patel2011-04-071-8/+18
| | | | | | match. llvm-svn: 129078
* Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner2011-04-071-0/+6
| | | | | | vector type (vectors of size 3). Also included test cases. llvm-svn: 129074
* Fixed a bug where missing EDInstInfo would causeSean Callanan2011-04-071-0/+3
| | | | | | tokenization to crash and burn. llvm-svn: 129051
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoadEli Friedman2011-04-071-21/+4
| | | | | | | | | | | is equivalent to any other relevant value; it isn't true in general. If it is equivalent, the LoopPromoter will tell the AST the equivalence. Also, delete the PreheaderLoad if it is unused. Chris, since you were the last one to make major changes here, can you check that this is sane? llvm-svn: 129049
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-3/+5
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Change -arm-divmod-libcall to a target neutral option.Evan Cheng2011-04-072-6/+7
| | | | llvm-svn: 129045
* Remove dead code. rdar://9221736.Evan Cheng2011-04-071-5/+0
| | | | llvm-svn: 129044
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
| | | | | | rdar://problem/9246650 llvm-svn: 129042
* Simplify. isIdenticalToWhenDefined() checks opcode.Devang Patel2011-04-071-4/+2
| | | | llvm-svn: 129041
* Set unnamed_addr on strings created through the IRBuilder.Nick Lewycky2011-04-071-0/+1
| | | | llvm-svn: 129040
* Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ↵Owen Anderson2011-04-061-1/+8
| | | | | | folded comparisons, just like ADD and SUB. llvm-svn: 129038
* Cleanups from Jim: remove redundant constraints and a dead FIXME.Owen Anderson2011-04-061-11/+5
| | | | llvm-svn: 129036
* While folding branch to a common destination into a predecessor, copy dbg ↵Devang Patel2011-04-061-4/+17
| | | | | | values also. llvm-svn: 129035
* Tidy up.Jim Grosbach2011-04-061-2/+1
| | | | llvm-svn: 129034
* A8.6.393Johnny Chen2011-04-061-26/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
* tidy up.Jim Grosbach2011-04-061-1/+1
| | | | llvm-svn: 129032
* Also account for the spill code that would be inserted in live-through ↵Jakob Stoklund Olesen2011-04-061-5/+16
| | | | | | blocks with interference. llvm-svn: 129030
* Abort the constraint calculation early when all positive bias is lost.Jakob Stoklund Olesen2011-04-061-33/+63
| | | | | | | Without any positive bias, there is nothing for the spill placer to to. It will spill everywhere. llvm-svn: 129029
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-1/+14
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* Fix comment to use llvm 2.x syntax.Nick Lewycky2011-04-061-1/+1
| | | | llvm-svn: 129025
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