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authorJohnny Chen <johnny.chen@apple.com>2011-04-07 18:33:19 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-04-07 18:33:19 +0000
commit194a2267add11d393cbb7f0bc2067e1410415231 (patch)
treee3e38fdd640201b770866461adbb76bc1b808117 /llvm/lib
parent2083c32f7aa6dfc3af66562dd5903d3e0b9eb59e (diff)
downloadbcm5719-llvm-194a2267add11d393cbb7f0bc2067e1410415231.tar.gz
bcm5719-llvm-194a2267add11d393cbb7f0bc2067e1410415231.zip
Add some more comments about checkings of invalid register numbers.
And two test cases. llvm-svn: 129090
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index bc0ba92d58e..f4fa3de2684 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1110,6 +1110,11 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// A8.6.3 ADC (register-shifted register)
// if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+ //
+ // This also accounts for shift instructions (register) where, fortunately,
+ // Inst{19-16} = 0b0000.
+ // A8.6.89 LSL (register)
+ // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if (decodeRd(insn) == 15 || decodeRn(insn) == 15 ||
decodeRm(insn) == 15 || decodeRs(insn) == 15)
return false;
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