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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-08 19:41:22 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-08 19:41:22 +0000 |
| commit | a9570f77d5999b8b27aa32e0e8baba0071a8558a (patch) | |
| tree | 1537121d07a06865666395c4822e0eeb9388cdf9 /llvm/lib | |
| parent | 875e0e46266de49d23b7f89a1bd89331b86aef9d (diff) | |
| download | bcm5719-llvm-a9570f77d5999b8b27aa32e0e8baba0071a8558a.tar.gz bcm5719-llvm-a9570f77d5999b8b27aa32e0e8baba0071a8558a.zip | |
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
PR9650
rdar://problem/9257565
llvm-svn: 129147
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 7900f9960ad..d4cd0879129 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -532,17 +532,18 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { switch (Opcode) { default: // Did we miss an opcode? - assert(0 && "Unexpected opcode!"); + DEBUG(errs() << "BadRegsMulFrm: unexpected opcode!"); return false; case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT: case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT: - case ARM::SMMLA: case ARM::SMMLS: case ARM::USADA8: + case ARM::SMMLA: case ARM::SMMLAR: case ARM::SMMLS: case ARM::SMMLSR: + case ARM::USADA8: if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) return true; return false; - case ARM::MUL: case ARM::SMMUL: case ARM::SMULBB: case ARM::SMULBT: - case ARM::SMULTB: case ARM::SMULTT: case ARM::SMULWB: case ARM::SMULWT: - case ARM::SMUAD: case ARM::SMUADX: + case ARM::MUL: case ARM::SMMUL: case ARM::SMMULR: + case ARM::SMULBB: case ARM::SMULBT: case ARM::SMULTB: case ARM::SMULTT: + case ARM::SMULWB: case ARM::SMULWT: case ARM::SMUAD: case ARM::SMUADX: // A8.6.167 SMLAD & A8.6.172 SMLSD case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX: case ARM::USAD8: @@ -562,14 +563,14 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { } // Multiply Instructions. -// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS, -// SMLAD, SMLADX, SMLSD, SMLSDX, USADA8 (for convenience): +// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLAR, +// SMMLS, SMMLAR, SMLAD, SMLADX, SMLSD, SMLSDX, and USADA8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12} // But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is // only for {d, n, m}. // -// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX, -// USAD8 (for convenience): +// MUL, SMMUL, SMMULR, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, +// SMUADX, and USAD8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} // // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, |
