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* [MC][ELF] Don't create relocations with section symbols for STB_LOCAL ifuncFangrui Song2019-06-071-0/+6
* [LV] Fix -Wunused-function after r362736Fangrui Song2019-06-071-0/+2
* AMDGPU: Don't count mask branch pseudo towards skip thresholdMatt Arsenault2019-06-071-10/+8
* AMDGPU: Insert skips for blocks with FLATMatt Arsenault2019-06-071-1/+2
* [PowerPC] Exploit the vector min/max instructionsNemanja Ivanovic2019-06-063-0/+65
* AMDGPU: Insert skip branches over return blocksMatt Arsenault2019-06-062-3/+4
* [DebugInfo] Incorrect debug info record generated for loop counter.Alexey Lapshin2019-06-061-19/+1
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-064-163/+107
* [X86] Make a bunch of merge masked binops commutable for loading folding.Craig Topper2019-06-061-8/+7
* [CFLGraph] Add support for unary fneg instruction.Craig Topper2019-06-061-0/+10
* [LV] Wrap LV illegality reporting in a function. NFC.Renato Golin2019-06-061-100/+120
* [AIX] Implement function descriptor on SDAGJason Liu2019-06-067-20/+82
* [InlineCost] Add support for unary fneg.Craig Topper2019-06-061-0/+23
* [LoopPred] Fix a bug in unconditional latch bailout introduced in r362284Philip Reames2019-06-061-2/+2
* [DAGCombine] MergeConsecutiveStores - improve non-temporal load\store handlin...Simon Pilgrim2019-06-061-7/+23
* Remove unused PPC.h includes under llvm/lib/Target/PowerPC.Dmitri Gribenko2019-06-063-4/+1
* [X86] Make masked floating point equality/ordered compares commutable for loa...Craig Topper2019-06-062-7/+17
* [DA] Add an option to control delinearization validity checksWhitney Tsang2019-06-061-10/+19
* [AIX] Implement call lowering with parameters could pass onto GPRsJason Liu2019-06-062-15/+83
* FileCheck [6/12]: Introduce numeric variable definitionThomas Preud'homme2019-06-061-124/+283
* AArch64] Handle ISD::LRINT and ISD::LLRINT for float16Adhemerval Zanella2019-06-061-0/+8
* Revert "[SCEV] Use wrap flags in InsertBinop"Benjamin Kramer2019-06-061-31/+18
* [AArch64] Handle ISD::LROUND and ISD::LLROUND for float16Adhemerval Zanella2019-06-061-0/+8
* Include what you use in LanaiAsmParser.cppDmitri Gribenko2019-06-061-1/+0
* [DAGCombine] Cleanup isNegatibleForFree/GetNegatedExpression. NFCI.Simon Pilgrim2019-06-061-20/+21
* [MIPS GlobalISel] Select sqrtPetar Avramovic2019-06-062-2/+3
* [MIPS GlobalISel] Select fabsPetar Avramovic2019-06-063-2/+13
* [MIPS GlobalISel] Select fpext and fptruncPetar Avramovic2019-06-062-0/+14
* [MIPS GlobalISel] Select floor and ceilPetar Avramovic2019-06-062-1/+12
* [SCEV] Use wrap flags in InsertBinopSam Parker2019-06-061-18/+31
* [AArch64][GlobalISel] Add manual selection support for G_ZEXTLOADs to s64.Amara Emerson2019-06-061-0/+23
* [AArch64][GlobalISel] Add the new changes to fix PR42129 that were supposed t...Amara Emerson2019-06-061-0/+5
* [X86] Don't turn avx masked.load with constant mask into masked.load+vselect ...Craig Topper2019-06-061-0/+3
* Revert "Revert "[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G...Amara Emerson2019-06-051-8/+96
* AMDGPU: Don't fix emergency stack slot at offset 0Matt Arsenault2019-06-052-26/+11
* [MSAN] Add unary FNeg visitor to the MemorySanitizerCameron McInally2019-06-051-0/+2
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-0520-207/+332
* Revert "[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G_SELECT ...Petr Hosek2019-06-051-96/+8
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-059-209/+218
* [CallSite removal] Refactoring llvm::InlineFunction APIsMircea Trofin2019-06-051-8/+2
* [InstCombine] simplify code for bitcast of insertelement; NFCSanjay Patel2019-06-051-5/+4
* NewGVN: Handle addrspacecastMatt Arsenault2019-06-051-2/+3
* [X86] Fix mistake that marked VADDSSrrb_Int/VADDSDrrb_Int/VMULSSrrb_Int/VMULS...Craig Topper2019-06-051-1/+1
* [LOOPINFO] Extend Loop object to add utilities to get the loop bounds,Whitney Tsang2019-06-051-0/+214
* InstCombine: correctly change byval type attribute alongside call args.Tim Northover2019-06-051-4/+20
* IR: make getParamByValType Just Work. NFC.Tim Northover2019-06-055-5/+11
* AMDGPU: Remove amdgpu-max-work-group-size attributeMatt Arsenault2019-06-051-10/+1
* AMDGPU: Fix using 2 different enums for same operand flagsMatt Arsenault2019-06-053-11/+8
* [WebAssembly] Limit PIC support to the Emscripten targetDan Gohman2019-06-051-2/+11
* [X86] Add the vector integer min/max instructions to isAssociativeAndCommutat...Craig Topper2019-06-051-0/+84
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