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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-07 00:14:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-07 00:14:55 +0000 |
| commit | c0edb8f5cf2f19496e44f59dce33d3e5695f5bf6 (patch) | |
| tree | ae264955f7fbbea0599f6f3dd7101cf64e6d944f /llvm/lib | |
| parent | 99ee81b1839aeee36a2c58e822f33e3101ceb7ad (diff) | |
| download | bcm5719-llvm-c0edb8f5cf2f19496e44f59dce33d3e5695f5bf6.tar.gz bcm5719-llvm-c0edb8f5cf2f19496e44f59dce33d3e5695f5bf6.zip | |
AMDGPU: Don't count mask branch pseudo towards skip threshold
llvm-svn: 362761
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInsertSkips.cpp | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp index 507c686e1cf..759e28e431f 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp @@ -92,15 +92,13 @@ INITIALIZE_PASS(SIInsertSkips, DEBUG_TYPE, char &llvm::SIInsertSkipsPassID = SIInsertSkips::ID; -static bool opcodeEmitsNoInsts(unsigned Opc) { - switch (Opc) { - case TargetOpcode::IMPLICIT_DEF: - case TargetOpcode::KILL: - case TargetOpcode::BUNDLE: - case TargetOpcode::CFI_INSTRUCTION: - case TargetOpcode::EH_LABEL: - case TargetOpcode::GC_LABEL: - case TargetOpcode::DBG_VALUE: +static bool opcodeEmitsNoInsts(const MachineInstr &MI) { + if (MI.isMetaInstruction()) + return true; + + // Handle target specific opcodes. + switch (MI.getOpcode()) { + case AMDGPU::SI_MASK_BRANCH: return true; default: return false; @@ -118,7 +116,7 @@ bool SIInsertSkips::shouldSkip(const MachineBasicBlock &From, for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end(); NumInstr < SkipThreshold && I != E; ++I) { - if (opcodeEmitsNoInsts(I->getOpcode())) + if (opcodeEmitsNoInsts(*I)) continue; // FIXME: Since this is required for correctness, this should be inserted |
