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* [InlineCost] Mark functions accessing varargs as not viable.Florian Hahn2018-01-281-6/+12
| | | | | | | | | | | | | This prevents functions accessing varargs from being inlined if they have the alwaysinline attribute. Reviewers: efriedma, rnk, davide Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D42556 llvm-svn: 323619
* [Support] Move DJB hash to support. NFCJonas Devlieghere2018-01-285-8/+25
| | | | | | | | | | | This patch moves the DJB hash to support. This is consistent with other hashing algorithms living there. The hash is used by the DWARF accelerator tables. We're doing this now because the hashing function is needed by dsymutil and we don't want to link against libBinaryFormat. Differential revision: https://reviews.llvm.org/D42594 llvm-svn: 323616
* [X86] Fix a crash that can occur in combineExtractVectorElt due to not ↵Craig Topper2018-01-281-2/+3
| | | | | | checking the width of a ConstantSDNode before calling getConstantOperandVal. llvm-svn: 323614
* [X86] Remove VPTESTM/VPTESTNM ISD opcodes. Use isel patterns matching cmpm ↵Craig Topper2018-01-285-93/+76
| | | | | | eq/ne with immallzeros. llvm-svn: 323612
* [X86] Add patterns for using masked vptestnmd for 256-bit vectors without VLX.Craig Topper2018-01-271-13/+24
| | | | | | We can widen the mask and extract it back down. llvm-svn: 323610
* [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a ↵Craig Topper2018-01-271-0/+7
| | | | | | | | | | | | zero vector. We can use the same input for both operands to get a free compare with zero. We already use this trick in a couple places where we explicitly create PTESTM with the same input twice. This generalizes it. I'm hoping to remove the ISD opcodes and move this to isel patterns like we do for scalar cmp/test. llvm-svn: 323605
* [X86] Remove X86ISD::PCMPGTM/PCMPEQM and instead just use X86ISD::PCMPM and ↵Craig Topper2018-01-275-43/+33
| | | | | | | | | | pattern match the immediate value during isel. Legalization is still biased to turn LT compares in to GT by swapping operands to avoid needing extra isel patterns to commute. I'm hoping to remove TESTM/TESTNM next and this should simplify that by making EQ/NE more similar. llvm-svn: 323604
* [X86][SSE] Simplify demanded elements from BROADCAST shuffle source.Simon Pilgrim2018-01-271-0/+30
| | | | | | | | If broadcasting from another shuffle, attempt to simplify it. We can probably generalize this a lot more (embedding in combineX86ShufflesRecursively), but BROADCAST is one of the more troublesome as it accepts inputs of different sizes to the result. llvm-svn: 323602
* Add IRBuilder API to create memcpy/memmove calls with differing source and ↵Daniel Neilson2018-01-272-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | dest alignments Summary: This change is step two in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. Step 3) Update Clang to use the new IRBuilder API. Step 4) Update Polly to use the new IRBuilder API. Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use getDestAlignment() and getSourceAlignment() instead. Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 323597
* [TargetLowering] Teach TargetLowering::SimplifySetCC to simplify setcc of ↵Craig Topper2018-01-271-14/+16
| | | | | | | | vXi1 vectors into logic ops. This transform was already being done for setcc of scalar i1. This extends it to vectors. llvm-svn: 323585
* [SelectionDAG] Make DAGTypeLegalizer::PromoteSetCCOperands handle ↵Craig Topper2018-01-271-4/+4
| | | | | | | | SETEQ/SETNE correctly for vector types. The code was using getValueSizeInBits and combining with the result of a call to DAG.ComputeNumSignBits. But for vector types getValueSizeInBits returns the width of the full vector while ComputeNumSignBits is going to give a number no larger than the width of a single element. So we should be using getScalarValueSizeInBits to get the element width. llvm-svn: 323583
* [GlobalISel][Legalizer] Convert the FP constants to the right APFloat type ↵Amara Emerson2018-01-271-1/+18
| | | | | | | | | | | for G_FCONSTANT. We weren't converting the immediate ConstantFP during legalization, which caused the wrong bit patterns to be emitted for half type FP constants. Fixes PR36106. llvm-svn: 323582
* Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements ↵Alexey Bataev2018-01-271-369/+131
| | | | | | | | as shuffle." This reverts commit r323530 to fix possible problems in users code. llvm-svn: 323581
* Revert "[SLP] Removed the warning about unused variable, NFC."Alexey Bataev2018-01-271-1/+1
| | | | | | This reverts commit r323533 to fix possible problems in users code. llvm-svn: 323580
* [InstrProfiling] Don't exit early when an unused intrinsic is foundVedant Kumar2018-01-271-3/+6
| | | | | | This fixes a think-o in r323574. llvm-svn: 323576
* [InstrProfiling] Improve compile time when there is no workVedant Kumar2018-01-261-2/+21
| | | | | | | When there are no uses of profiling intrinsics in a module, and there's no coverage data to lower, InstrProfiling has no work to do. llvm-svn: 323574
* [X86] Use vpternlog to implement vector not under AVX512.Craig Topper2018-01-261-0/+36
| | | | | | | | Previously we had to materialize all 1s in a register using vpternlog or pcmpeq and then xor with that. By using vpternlog directly we can do it in one operation. This is implemented using isel patterns, but we should maybe consider creating a generalized vpternlog combiner. llvm-svn: 323572
* [InstCombine] Preserve debug values for eliminable castsVedant Kumar2018-01-261-1/+15
| | | | | | | | | | | | | | | | | A cast from A to B is eliminable if its result is casted to C, and if the pair of casts could just be expressed as a single cast. E.g here, %c1 is eliminable: %c1 = zext i16 %A to i32 %c2 = sext i32 %c1 to i64 InstCombine optimizes away eliminable casts. This patch teaches it to insert a dbg.value intrinsic pointing to the final result, so that local variables pointing to the eliminable result are preserved. Differential Revision: https://reviews.llvm.org/D42566 llvm-svn: 323570
* Inline variable only used within assert.Richard Trieu2018-01-261-2/+1
| | | | llvm-svn: 323569
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-263-27/+55
| | | | llvm-svn: 323568
* [Hexagon] Make sure that offset on globals matches alignment requirementsKrzysztof Parzyszek2018-01-261-14/+40
| | | | | | | | | | | | | A correctly aligned address may happen to be separated into a variable part and a constant part, where the constant part does not match the alignment needed in a load/store that uses this address. Such a constant cannot be used as an immediate offset in an indexed instruction. When lowering a global address, make sure that if there is an offset folded into the global, the offset is valid for all uses in load/store instructions. llvm-svn: 323562
* [Hexagon] Replace multiple vector extracts with store-load combinationsKrzysztof Parzyszek2018-01-263-0/+176
| | | | llvm-svn: 323561
* [LivePhysRegs] Preserve pristine regs in blocks with no successors.Eli Friedman2018-01-261-2/+2
| | | | | | | | | | | | | | | One common source of blocks with no successors is calls to noreturn functions; we want to preserve pristine registers in case they throw an exception. The whole pristine register thing is messy (we should really prefer to explicitly model registers), but this fills a hole in the model for now. Fixes https://bugs.llvm.org/show_bug.cgi?id=36073. Differential Revision: https://reviews.llvm.org/D42509 llvm-svn: 323559
* [Support] Move PrintEscapedString into the library its declaration is inBenjamin Kramer2018-01-262-10/+10
| | | | llvm-svn: 323558
* [X86] Unbreak the build.Benjamin Kramer2018-01-261-1/+2
| | | | | | | | X86ISelLowering.cpp:34130:5: error: return type 'llvm::SDValue' must match previous return type 'const llvm::SDValue' when lambda expression has unspecified explicit return type llvm-svn: 323557
* [X86] Allow any_extend to be combined with setcc on VLX targets.Craig Topper2018-01-261-0/+8
| | | | | | For VLX target getSetccResultType returns vXi1 which prevents the target independent DAG combine from doing this tranform itself. llvm-svn: 323555
* [X86][AVX512] Add combining support for X86ISD::VTRUNCSSimon Pilgrim2018-01-261-7/+45
| | | | | | | | Similar to the existing support for X86ISD::VTRUNCUS. Differential Revision: https://reviews.llvm.org/D42544 llvm-svn: 323553
* [SelectionDAGISel] Add a debug print before call to Select. Adjust where ↵Craig Topper2018-01-2612-44/+5
| | | | | | | | | | | | blank lines are printed during isel process to make things more sensibly grouped. Previously some targets printed their own message at the start of Select to indicate what they were selecting. For the targets that didn't, it means there was no print of the root node before any custom handling in the target executed. So if the target did something custom and never called SelectNodeCommon, no print would be made. For the targets that did print a message in Select, if they didn't custom handle a node SelectNodeCommon would reprint the root node before walking the isel table. It seems better to just print the message before the call to Select so all targets behave the same. And then remove the root node printing from SelectNodeCommon and just leave a message that says we're starting the table search. There were also some oddities in blank line behavior. Usually due to a \n after a call to SelectionDAGNode::dump which already inserted a new line. llvm-svn: 323551
* [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.Craig Topper2018-01-261-0/+1
| | | | | | gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546 llvm-svn: 323550
* [Hexagon] Fix an incorrect assertion in HexagonConstExtendersKrzysztof Parzyszek2018-01-261-8/+14
| | | | llvm-svn: 323548
* [DWARF] Generate DWARF v5 string offsets tables along with strx* index forms.Wolfgang Pieb2018-01-269-38/+181
| | | | | | | | | | | | Summary: This is the producer side for DWARF v5 string offsets tables. The reader/consumer side was committed with r321295. All compile and type units in a module share a contribution to the string offsets table. Indirect strings use the strx{1,2,3,4} index forms. Reviewers: dblaikie, aprantl, JDevliegehere Differential Revision: https://reviews.llvm.org/D42021 llvm-svn: 323546
* [x86] fix typo in comment; NFCSanjay Patel2018-01-261-1/+1
| | | | llvm-svn: 323545
* [X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support for VPERMILPV to ↵Simon Pilgrim2018-01-261-0/+7
| | | | | | | | v4i32/v4f32 Extension to D42431, adding support for v4i32/v4f32 as well as v2i64/v2f64 now that D42308 has landed llvm-svn: 323542
* [X86][SSE] Don't colaesce v4i32 extractsSimon Pilgrim2018-01-261-96/+1
| | | | | | | | | | We currently coalesce v4i32 extracts from all 4 elements to 2 v2i64 extracts + shifts/sign-extends. This seems to have been added back in the days when we tended to spill vectors and reload scalars, or ended up with repeated shuffles moving everything down to 0'th index. I don't think either of these are likely these days as we have better EXTRACT_VECTOR_ELT and VECTOR_SHUFFLE handling, and the existing code tends to make it very difficult for various vector and load combines. Differential Revision: https://reviews.llvm.org/D42308 llvm-svn: 323541
* [X86][SSE] Drop PMADDWD in lowerMulSimon Pilgrim2018-01-261-7/+0
| | | | | | As mentioned in D42258, we don't need this any more llvm-svn: 323540
* [DAG] Teach findBaseOffset to interpret indexes of indexed memory operationsNirav Dave2018-01-261-8/+35
| | | | | | Indexed outputs are addition / subtractions and can be interpreted as such. llvm-svn: 323539
* [AMDGPU][MC] Added validation of image dst/data size (must match dmask and tfe)Dmitry Preobrazhensky2018-01-261-0/+61
| | | | | | | | | See bug 36000: https://bugs.llvm.org/show_bug.cgi?id=36000 Differential Revision: https://reviews.llvm.org/D42483 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 323538
* [MIPS] Don't crash on unsized extern types with -mgpoptAlexander Richardson2018-01-261-0/+7
| | | | | | | | | | | | | | Summary: This fixes an assertion when building the FreeBSD MIPS64 kernel. Reviewers: atanasyan, sdardis, emaste Reviewed By: sdardis Subscribers: krytarowski, llvm-commits Differential Revision: https://reviews.llvm.org/D42571 llvm-svn: 323536
* [DAGCombine] reduceBuildVecToShuffle - ensure EXTRACT_VECTOR_ELT index is in ↵Simon Pilgrim2018-01-261-1/+5
| | | | | | | | range From OSS Fuzz Test Case #5688 llvm-svn: 323535
* [AMDGPU][MC] Added support of 64-bit image atomicsDmitry Preobrazhensky2018-01-265-17/+115
| | | | | | | | | See bug 35998: https://bugs.llvm.org/show_bug.cgi?id=35998 Differential Revision: https://reviews.llvm.org/D42469 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 323534
* [SLP] Removed the warning about unused variable, NFC.Alexey Bataev2018-01-261-1/+1
| | | | llvm-svn: 323533
* [SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.Alexey Bataev2018-01-261-131/+369
| | | | | | | | | | | | | | | | | Summary: If the same value is going to be vectorized several times in the same tree entry, this entry is considered to be a gather entry and cost of this gather is counter as cost of InsertElementInstrs for each gathered value. But we can consider these elements as ShuffleInstr with SK_PermuteSingle shuffle kind. Reviewers: spatel, RKSimon, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38697 llvm-svn: 323530
* [AMDGPU][MC] Enabled disassembler for image atomic operationsDmitry Preobrazhensky2018-01-261-12/+16
| | | | | | | | | See bug 35988: https://bugs.llvm.org/show_bug.cgi?id=35988 Differential Revision: https://reviews.llvm.org/D42186 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 323527
* [X86] Cleanup SDLoc arguments as mentioned on D42544Simon Pilgrim2018-01-261-6/+7
| | | | llvm-svn: 323526
* [MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih2018-01-264-0/+20
| | | | | | | | | | Add support for printing / parsing the addrspace of a MachineMemOperand. Fixes PR35970. Differential Revision: https://reviews.llvm.org/D42502 llvm-svn: 323521
* [AMDGPU] fix LDS f32 intrinsicsDaniil Fukalov2018-01-263-22/+25
| | | | | | | | | | | | - using qualified pointer addrspace in intrinsics class to avoid .f32 mangling - changed too common atomic mangling to ds - added missing intrinsics to AMDGPUTTIImpl::getTgtMemIntrinsic Reviewed by: b-sumner Differential Revision: https://reviews.llvm.org/D42383 llvm-svn: 323516
* [CallSiteSplitting] Fix infinite loop when recording conditions.Florian Hahn2018-01-261-1/+2
| | | | | | | | | Fix infinite loop when recording conditions by correctly marking basic blocks as visited. Fixes https://bugs.llvm.org/show_bug.cgi?id=36105 llvm-svn: 323515
* [ARM] Accept a subset of Thumb GPR register class when emitting an SP-relativeMomchil Velikov2018-01-261-2/+2
| | | | | | | | | | | | | load instruction The function `Thumb1InstrInfo::loadRegFromStackSlot` accepts only the `tGPR` register class. The function serves to emit a `tLDRspi` instruction and certainly any subset of the `tGPR` register class is a valid destination of the load. Differential revision: https://reviews.llvm.org/D42535 llvm-svn: 323514
* [ARM] Armv8.2-A FP16 code generation (part 1/3)Sjoerd Meijer2018-01-269-28/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the groundwork for Armv8.2-A FP16 code generation . Clang passes and returns _Float16 values as floats, together with the required bitconverts and truncs etc. to implement correct AAPCS behaviour, see D42318. We will implement half-precision argument passing/returning lowering in the ARM backend soon, but for now this means that this: _Float16 sub(_Float16 a, _Float16 b) { return a + b; } gets lowered to this: define float @sub(float %a.coerce, float %b.coerce) { entry: %0 = bitcast float %a.coerce to i32 %tmp.0.extract.trunc = trunc i32 %0 to i16 %1 = bitcast i16 %tmp.0.extract.trunc to half <SNIP> %add = fadd half %1, %3 <SNIP> } When FullFP16 is *not* supported, we don't make f16 a legal type, and we get legalization for "free", i.e. nothing changes and everything works as before. And also f16 argument passing/returning is handled. When FullFP16 is supported, we do make f16 a legal type, and have 2 places that we need to patch up: f16 argument passing and returning, which involves minor tweaks to avoid unnecessary code generation for some bitcasts. As a "demonstrator" that this works for the different FP16, FullFP16, softfp modes, etc., I've added match rules to the VSUB instruction description showing that we can codegen this instruction from IR, but more importantly, also to some conversion instructions. These conversions were causing issue before in the FP16 and FullFP16 cases. I've also added match rules to the VLDRH and VSTRH desriptions, so that we can actually compile the entire half-precision sub code example above. This showed that these loads and stores had the wrong addressing mode specified: AddrMode5 instead of AddrMode5FP16, which turned out not be implemented at all, so that has also been added. This is the minimal patch that shows all the different moving parts. In patch 2/3 I will add some efficient lowering of bitcasts, and in 2/3 I will add the remaining Armv8.2-A FP16 instruction descriptions. Thanks to Sam Parker and Oliver Stannard for their help and reviews! Differential Revision: https://reviews.llvm.org/D38315 llvm-svn: 323512
* [NFC] fix trivial typos in comments and documentsHiroshi Inoue2018-01-2613-14/+14
| | | | | | "in in" -> "in", "on on" -> "on" etc. llvm-svn: 323508
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